From patchwork Mon Apr 29 12:09:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ravi Gunasekaran X-Patchwork-Id: 13646723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A5D5C4345F for ; Mon, 29 Apr 2024 12:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0YTxocZl+15aI/hybwj/43ccz0rSNGz93S3FJmnYQBw=; b=zvVk3ZkSKmspz5 EkF+Nl/hLRL4KwhH/DJK4a+CIjhXPORxJjvhmYg6QQfpHlUc3Ymn8AcVC/uhwLYAwGl2eZYZgpGnD dcVrBRu1e9ymSVXYq3FKRuvgs0maKLAEFdpDFl531tnXvtb6GLetpHGtgqSGKyiTqUXqTQpO4kXuF LnoS4+or03fOnT1ynfNUlQ/OVSzJfgzuN7stMJZ7/JBx25D4ZB7bRwCkeBWTWN2VBTRwyZFK6zf/E cmbv3RoZgT9pFhKerSI+6pf3+nxTMZTxP2F40TrBY+0A6sTc66kUFnkHUV3CeVsud8QgFYSK/9mwA dXW0LJUF2Wlhz/pUc8KQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1PpU-00000002c73-1MMH; Mon, 29 Apr 2024 12:09:56 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1PpL-00000002c0h-3MSR for linux-arm-kernel@lists.infradead.org; Mon, 29 Apr 2024 12:09:49 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 43TC9fKi090068; Mon, 29 Apr 2024 07:09:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1714392581; bh=rdw8evLwWtWg4TxCSZv2WlOmo6cXgGwlewjHR7pWkyc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RDNfN7hQNXEt58RALhNoEd7AlIlVyG00VjK9H5lRpVAJkeqRLvv2lkhDQmU7XqTg5 6CZmIibl4Z2cWBVNW4VMgjefimo66WNzucJFFbjNI5YbkcS4gEPF8a+3L2jWfLUzrp aWqFRxnX5BoB/D05mmWo1xEV9F84mvCf4vaf0FB0= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 43TC9fl0099105 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Apr 2024 07:09:41 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Apr 2024 07:09:40 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Apr 2024 07:09:40 -0500 Received: from uda0500640.dal.design.ti.com (uda0500640.dhcp.ti.com [172.24.227.88]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 43TC9XrF012367; Mon, 29 Apr 2024 07:09:37 -0500 From: Ravi Gunasekaran To: , CC: , , , , , , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-j722s: Add support for SERDES0 Date: Mon, 29 Apr 2024 17:39:30 +0530 Message-ID: <20240429120932.11456-2-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240429120932.11456-1-r-gunasekaran@ti.com> References: <20240429120932.11456-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_050947_999545_6A48A8E0 X-CRM114-Status: GOOD ( 11.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add SERDES0 and its wrapper description to support USB3 and SGMII interfaces. Signed-off-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index c75744edb143..beba5a3ea6cc 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include "k3-am62p5.dtsi" @@ -75,6 +76,50 @@ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; }; + + serdes_refclk: clock-cmnrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; }; /* Main domain overrides */ @@ -83,6 +128,15 @@ ti,interrupt-ranges = <7 71 21>; }; +&main_conf { + serdes0_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ + }; +}; + &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>;