| Message ID | 20240429152207.479221-18-james.clark@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: Use per-sink trace ID maps for Perf sessions | expand |
On 29/04/2024 16:22, James Clark wrote: > In per-cpu mode there are multiple aux buffers and each one has a > fixed sink, so the hw ID mappings which only need to be emitted once > for each buffer, even with the new per-sink trace ID pools. > > But in per-thread mode there is only a single buffer which can be > written to from any sink with now potentially overlapping trace IDs, so > hw ID mappings need to be re-emitted every time the sink changes. > > This will require a change in Perf to track this so it knows which > decode tree to use for each segment of the buffer. In theory it's also > possible to look at the CPU ID on the AUX records, but this is more > consistent with the existing system, and allows for correct decode using > either mechanism. > > Signed-off-by: James Clark <james.clark@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm-perf.c | 14 ++++++++++++++ > drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ > 2 files changed, 16 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index f07173aa4d66..08f3958f9367 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -499,6 +499,20 @@ static void etm_event_start(struct perf_event *event, int flags) > &sink->perf_id_map)) > goto fail_disable_path; > > + /* > + * In per-cpu mode there are multiple aux buffers and each one has a > + * fixed sink, so the hw ID mappings which only need to be emitted once > + * for each buffer. > + * > + * But in per-thread mode there is only a single buffer which can be > + * written to from any sink with potentially overlapping trace IDs, so > + * hw ID mappings need to be re-emitted every time the sink changes. > + */ > + if (event->cpu == -1 && event_data->last_sink_hwid != sink) { > + cpumask_clear(&event_data->aux_hwid_done); > + event_data->last_sink_hwid = sink; > + } > + With the traceid caching in the event_data per-cpu , we could avoid this step ? Suzuki
On 07/05/2024 13:05, Suzuki K Poulose wrote: > On 29/04/2024 16:22, James Clark wrote: >> In per-cpu mode there are multiple aux buffers and each one has a >> fixed sink, so the hw ID mappings which only need to be emitted once >> for each buffer, even with the new per-sink trace ID pools. >> >> But in per-thread mode there is only a single buffer which can be >> written to from any sink with now potentially overlapping trace IDs, so >> hw ID mappings need to be re-emitted every time the sink changes. >> >> This will require a change in Perf to track this so it knows which >> decode tree to use for each segment of the buffer. In theory it's also >> possible to look at the CPU ID on the AUX records, but this is more >> consistent with the existing system, and allows for correct decode using >> either mechanism. >> >> Signed-off-by: James Clark <james.clark@arm.com> >> --- >> drivers/hwtracing/coresight/coresight-etm-perf.c | 14 ++++++++++++++ >> drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ >> 2 files changed, 16 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c >> b/drivers/hwtracing/coresight/coresight-etm-perf.c >> index f07173aa4d66..08f3958f9367 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c >> @@ -499,6 +499,20 @@ static void etm_event_start(struct perf_event >> *event, int flags) >> &sink->perf_id_map)) >> goto fail_disable_path; >> + /* >> + * In per-cpu mode there are multiple aux buffers and each one has a >> + * fixed sink, so the hw ID mappings which only need to be >> emitted once >> + * for each buffer. >> + * >> + * But in per-thread mode there is only a single buffer which can be >> + * written to from any sink with potentially overlapping trace >> IDs, so >> + * hw ID mappings need to be re-emitted every time the sink changes. >> + */ >> + if (event->cpu == -1 && event_data->last_sink_hwid != sink) { >> + cpumask_clear(&event_data->aux_hwid_done); >> + event_data->last_sink_hwid = sink; >> + } >> + > > With the traceid caching in the event_data per-cpu , we could avoid this > step ? > > Suzuki > > I don't think so, this is to inform the tool that the mappings have changed if the tool doesn't want to follow switch events. Unless I'm missing something, moving where the trace ids are stored doesn't mean that they will be re-sent when the mappings change?
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index f07173aa4d66..08f3958f9367 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -499,6 +499,20 @@ static void etm_event_start(struct perf_event *event, int flags) &sink->perf_id_map)) goto fail_disable_path; + /* + * In per-cpu mode there are multiple aux buffers and each one has a + * fixed sink, so the hw ID mappings which only need to be emitted once + * for each buffer. + * + * But in per-thread mode there is only a single buffer which can be + * written to from any sink with potentially overlapping trace IDs, so + * hw ID mappings need to be re-emitted every time the sink changes. + */ + if (event->cpu == -1 && event_data->last_sink_hwid != sink) { + cpumask_clear(&event_data->aux_hwid_done); + event_data->last_sink_hwid = sink; + } + /* * output cpu / trace ID in perf record, once for the lifetime * of the event. diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 744531158d6b..bd4553b2a1ec 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -52,6 +52,7 @@ struct etm_filters { * @snk_config: The sink configuration. * @cfg_hash: The hash id of any coresight config selected. * @path: An array of path, each slot for one CPU. + * @last_sink_hwid: Last sink that a hwid was emitted for. */ struct etm_event_data { struct work_struct work; @@ -60,6 +61,7 @@ struct etm_event_data { void *snk_config; u32 cfg_hash; struct list_head * __percpu *path; + struct coresight_device *last_sink_hwid; }; int etm_perf_symlink(struct coresight_device *csdev, bool link);
In per-cpu mode there are multiple aux buffers and each one has a fixed sink, so the hw ID mappings which only need to be emitted once for each buffer, even with the new per-sink trace ID pools. But in per-thread mode there is only a single buffer which can be written to from any sink with now potentially overlapping trace IDs, so hw ID mappings need to be re-emitted every time the sink changes. This will require a change in Perf to track this so it knows which decode tree to use for each segment of the buffer. In theory it's also possible to look at the CPU ID on the AUX records, but this is more consistent with the existing system, and allows for correct decode using either mechanism. Signed-off-by: James Clark <james.clark@arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 14 ++++++++++++++ drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ 2 files changed, 16 insertions(+)