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AJvYcCVNyOMV1NthiUEDA3M9KBQEivmbYXUWkdrmGF/NUHSQuqIKrgd6hGrGHSalKXdvxChWWhEVqvNC7t+9ksJSLs9btx3TzuqPtRk6wOAhlyAjztLPYH4= X-Gm-Message-State: AOJu0Yx6z76PHs1XvBLCzYBIfdpf4SOlB104eQG9Ql71VTEqSpt/X9dH esTExcnHCYeV+dUrDQI6rgE6AEZpUytWs8sj7XY9FWwQv/VLQeCexDFy8+jN8f0= X-Google-Smtp-Source: AGHT+IEEpqR6LOLNxdPkqMtyOYbTgdIvTDuuBru9JEjSe3nJuXIJsw3V8KyaGY6kpiknSGkfBm1TCw== X-Received: by 2002:a05:600c:4687:b0:41b:82ba:7997 with SMTP id p7-20020a05600c468700b0041b82ba7997mr2226875wmo.3.1714486493857; Tue, 30 Apr 2024 07:14:53 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:f162:7aca:a805:2c2f]) by smtp.gmail.com with ESMTPSA id r10-20020a05600c458a00b0041bf3a716b9sm11593517wmo.34.2024.04.30.07.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 07:14:53 -0700 (PDT) From: Peter Griffin To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin Subject: [PATCH v5 2/3] arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes Date: Tue, 30 Apr 2024 15:14:44 +0100 Message-ID: <20240430141445.2688499-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.45.0.rc0.197.gbae5840b3b-goog In-Reply-To: <20240430141445.2688499-1-peter.griffin@linaro.org> References: <20240430141445.2688499-1-peter.griffin@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240430_071456_306275_036B6378 X-CRM114-Status: GOOD ( 10.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin Acked-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9f7635a7928e..16e1c474e8dd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1332,6 +1332,42 @@ pinctrl_hsi2: pinctrl@14440000 { interrupts = ; }; + ufs_0: ufs@14700000 { + compatible = "google,gs101-ufs"; + reg = <0x14700000 0x200>, + <0x14701100 0x200>, + <0x14780000 0xa000>, + <0x14600000 0x100>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + clock-names = "core_clk", "sclk_unipro_main", "fmp", + "aclk", "pclk", "sysreg"; + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names = "default"; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&sysreg_hsi2 0x710>; + status = "disabled"; + }; + + ufs_0_phy: phy@14704000 { + compatible = "google,gs101-ufs-phy"; + reg = <0x14704000 0x3000>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&ext_24_5m>; + clock-names = "ref_clk"; + status = "disabled"; + }; + cmu_apm: clock-controller@17400000 { compatible = "google,gs101-cmu-apm"; reg = <0x17400000 0x8000>;