| Message ID | 20240513-rzn1-gmac1-v7-7-6acf58b5440d@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: stmmac: Add support for RZN1 GMAC devices | expand |
On Mon, May 13, 2024 at 9:24 AM Romain Gantois <romain.gantois@bootlin.com> wrote: > From: Clément Léger <clement.leger@bootlin.com> > > The r9a06g032 SoC of the RZ/N1 family features two GMAC devices named > GMAC1/2, that are based on Synopsys cores. GMAC1 is connected to a > RGMII/RMII converter that is already described in this device tree. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > [rgantois: commit log] > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Romain Gantois <romain.gantois@bootlin.com> Thanks, will queue in renesas-devel for v6.11. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index fa63e1afc4ef4..57c730f43442e 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -316,6 +316,24 @@ dma1: dma-controller@40105000 { data-width = <8>; }; + gmac1: ethernet@44000000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44000000 0x2000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + pcs-handle = <&mii_conv1>; + status = "disabled"; + }; + gmac2: ethernet@44002000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44002000 0x2000>;