diff mbox series

[v2,1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes

Message ID 20240520101149.3243151-2-s-vadapalli@ti.com (mailing list archive)
State New, archived
Headers show
Series Add PCIe DT support for TI's J784S4 SoC | expand

Commit Message

Siddharth Vadapalli May 20, 2024, 10:11 a.m. UTC 
TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely
PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of
these PCIe instances.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v1:
https://lore.kernel.org/r/20240129114749.1197579-2-s-vadapalli@ti.com/
Changes since v1:
- Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the "scm_conf" node
  in order to reuse the existing "ti,syscon-pcie-ctrl" property without
  having to map the entire "scm_conf" region for configuring the PCIe
  Control registers pointed to by the "pcie0_ctrl" and "pcie1_ctrl"
  nodes.

 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 94 ++++++++++++++++++++++
 1 file changed, 94 insertions(+)

Comments

Francesco Dolcini May 21, 2024, 8:09 p.m. UTC | #1 
On Mon, May 20, 2024 at 03:41:47PM +0530, Siddharth Vadapalli wrote:
> TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely
> PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of
> these PCIe instances.

What about PCIE2? J784S4 has 3 PCIe instances, it would be beneficial to
add all 3, not just the first twos.

Francesco
Siddharth Vadapalli May 22, 2024, 10:21 a.m. UTC | #2 
On Tue, May 21, 2024 at 10:09:09PM +0200, Francesco Dolcini wrote:
> On Mon, May 20, 2024 at 03:41:47PM +0530, Siddharth Vadapalli wrote:
> > TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely
> > PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of
> > these PCIe instances.
> 
> What about PCIE2? J784S4 has 3 PCIe instances, it would be beneficial to
> add all 3, not just the first twos.

Thank you for reviewing the patch. I agree that it was incorrect for me
to mention that J784S4 has two instances of PCIe. It actually has 4
instances as mentioned in the Excel Sheet provided along with the
Technical Reference Manual at:
https://www.ti.com/lit/zip/spruj52
namely PCIe0, PCIe1, PCIe2 and PCIe3.

Since the J784S4 EVM has only PCIe0 and PCIe1 instances of PCIe brought
out, I was able to test them and therefore added support for only those
two instances in this series. However I do agree that all 4 should be
added to the SoC file (k3-j784s4-main.dtsi) for the sake of completeness
in terms of describing the SoC, while the Board file (k3-j784s4-evm.dts)
can still contain just PCIe0 and PCIe1 as those are the ones brought out
on the board. I will implement your suggestion in the v3 series.

Regards,
Siddharth.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 6a4554c6c9c1..c99bd1284c28 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -48,6 +48,16 @@  scm_conf: bus@100000 {
 		#size-cells = <1>;
 		ranges = <0x00 0x00 0x00100000 0x1c000>;
 
+		pcie0_ctrl: pcie0-ctrl@4070 {
+			compatible = "ti,j784s4-pcie-ctrl", "syscon";
+			reg = <0x4070 0x4>;
+		};
+
+		pcie1_ctrl: pcie1-ctrl@4074 {
+			compatible = "ti,j784s4-pcie-ctrl", "syscon";
+			reg = <0x4074 0x4>;
+		};
+
 		serdes_ln_ctrl: mux-controller@4080 {
 			compatible = "reg-mux";
 			reg = <0x00004080 0x30>;
@@ -907,6 +917,90 @@  main_sdhci1: mmc@4fb0000 {
 		status = "disabled";
 	};
 
+	pcie0_rc: pcie@2900000 {
+		compatible = "ti,j784s4-pcie-host";
+		reg = <0x00 0x02900000 0x00 0x1000>,
+		      <0x00 0x02907000 0x00 0x400>,
+		      <0x00 0x0d000000 0x00 0x00800000>,
+		      <0x00 0x10000000 0x00 0x00001000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+		device_type = "pci";
+		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+		max-link-speed = <3>;
+		num-lanes = <4>;
+		power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 332 0>;
+		clock-names = "fck";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0xff>;
+		vendor-id = <0x104c>;
+		device-id = <0xb012>;
+		msi-map = <0x0 &gic_its 0x0 0x10000>;
+		dma-coherent;
+		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
+			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+				<0 0 0 2 &pcie0_intc 0>,
+				<0 0 0 3 &pcie0_intc 0>,
+				<0 0 0 4 &pcie0_intc 0>;
+		status = "disabled";
+
+		pcie0_intc: interrupt-controller {
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+
+	pcie1_rc: pcie@2910000 {
+		compatible = "ti,j784s4-pcie-host";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x00001000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		device_type = "pci";
+		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+		max-link-speed = <3>;
+		num-lanes = <4>;
+		power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 333 0>;
+		clock-names = "fck";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0xff>;
+		vendor-id = <0x104c>;
+		device-id = <0xb012>;
+		msi-map = <0x0 &gic_its 0x10000 0x10000>;
+		dma-coherent;
+		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
+			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+				<0 0 0 2 &pcie1_intc 0>,
+				<0 0 0 3 &pcie1_intc 0>,
+				<0 0 0 4 &pcie1_intc 0>;
+		status = "disabled";
+
+		pcie1_intc: interrupt-controller {
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+
 	serdes_wiz0: wiz@5060000 {
 		compatible = "ti,j784s4-wiz-10g";
 		#address-cells = <1>;