From patchwork Tue May 21 06:25:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13668927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2618AC25B74 for ; Tue, 21 May 2024 06:17:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Cc:To:In-Reply-To: References:Message-Id:Subject:Date:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=0oO75BixG2pZVujsNj9wl8bfoMnAr+j6K+V0PCz376Q=; b=D9drx2/ANNIiturbcETJ8UE2g6 lO2+SrT25ZOjxJCeuC5Cp856xfQm3f7nccvB1Qz0B9uRkzwqnxNgACehw4GRFX2OUW3Isy5zuMj6D NBtL10d5ttzyTIhRr1FnkUj6nTxeHGZSgY1STshsbGaquUe+QNV6gixQcI5VRaK6eM6sA2OOTo83k +m2z8CWe1c7nM9diaV+t+iXbfgF6RcdizKtLaf4TvKWS5FIUbaw/i4vuSTLbWIhAV1VA033XykwPe 8VkifF9w/aifHnPv5OhwO91gYLq9rMQSrGllbObI27ZUkJtz8GXql1pbW/QM7b18zwOs2/rpPk/AZ mVWKMarQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s9Ioa-0000000GS41-4ApA; Tue, 21 May 2024 06:17:37 +0000 Received: from mail-am6eur05on20600.outbound.protection.outlook.com ([2a01:111:f403:2612::600] helo=EUR05-AM6-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s9IoX-0000000GRz5-0iH1 for linux-arm-kernel@lists.infradead.org; Tue, 21 May 2024 06:17:35 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Xh0ACmYRykvUPveYwIJy09P/UufZBl/o2wB8wOw8Oc0TdXhE+6BXMnVpLPLVojl3DUaR8pFcD/IrASLCosu2ur0p5J8axJSZTZQtykVXPoj0qybN99008yFk8lkquILs/ZRnFxGKNiKST3diegeC9n14Bu2YVe99972tIgGlcQdfkovRU2oCLw5XvUzFZ+qcUc9Cu2m9nA3OFqXJlPcUw5m+DfsHviuNBMqx+LhAxxCUqRnw/ey0jBdtetzZ4Tf2s9NYarA33WB8JptiXyFgZHvF50jcphjBwBKmpwj8H2hVKh9OL+loxw2RJCe6/6Mw9QmwTNCCLQgkKeYgRA/r9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KmD0YFXDYJh6S05DmzfZsFHpX49Q7e8f8bFQm4qkEvE=; b=BQ0gKMpmLEZcs1f2z87p3Xy1kHMdC4NRTmWvVCNgCwdWxX9UpK4Y6cwaEb8rAtx3Aqy6DY7QeJIYrX/23IGNmsgi/SpkVyGgkNr3Jmxkjp3XRXr5bH8b8ediB8ax98GCCqYA6VgM4hddpJYwnBCjXGRvwmqLUrsODix9XmKaQaJ7NaO7nn8W2MyhgiArJzNbWaXyYghtCVG+Sqo1U3yaiPoFPZvv5HahK+yfPFVlcjleODgUV8koT/8DmmgmxVZh8ERDxqa5guiuhoIIH3G8hhCNO73zjSnMv4g2N6PvxNUQSLhO3/rRf4U1HsUYpQksUSirFTevlaFKD19OxMlH0Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com; dkim=pass header.d=oss.nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com; s=selector2-NXP1-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KmD0YFXDYJh6S05DmzfZsFHpX49Q7e8f8bFQm4qkEvE=; b=Fm2o0gXyK3sf9VkLx4+deL8gdW8nGwMJlod5gHcNhVSMKVay/PNsKgdBG7TV0mtS83zroykf1y31YaPs1qg8eKHTcZkdYZnnlSkal5UkKkCF5sCLnZ1GMYNui81XnVA9r05qUmHqJvpkxh/PT+MOMb9o3ZFdo58bHzPWxH70M/g= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by GVXPR04MB10705.eurprd04.prod.outlook.com (2603:10a6:150:223::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7587.36; Tue, 21 May 2024 06:17:20 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::557f:6fcf:a5a7:981c%6]) with mapi id 15.20.7587.035; Tue, 21 May 2024 06:17:20 +0000 From: "Peng Fan (OSS)" Date: Tue, 21 May 2024 14:25:59 +0800 Subject: [PATCH 3/3] pinctrl: imx: support SCMI pinctrl protocol for i.MX95 Message-Id: <20240521-pinctrl-scmi-imx95-v1-3-9a1175d735fd@nxp.com> References: <20240521-pinctrl-scmi-imx95-v1-0-9a1175d735fd@nxp.com> In-Reply-To: <20240521-pinctrl-scmi-imx95-v1-0-9a1175d735fd@nxp.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Linus Walleij , Dong Aisheng , Jacky Bai Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-gpio@vger.kernel.org, Peng Fan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716272771; l=12502; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=l+00njiRg3DuMhS2ZjmxnpkN5gbVjq8Dvu96gz/WGts=; b=FvJBdBNtn/WV7NZIirZThYu9UIkMTNlIsrNwYM2bYxhjMrVwFZnH/XzNySq0LzbiJfktl3AlD +PQL1Kv+WChDlWzZaym9ZDd0KD/KwAv2cMtMvW+iWQUDAeJrbdNHXho X-Developer-Key: i=peng.fan@nxp.com; a=ed25519; pk=I4sJg7atIT1g63H7bb5lDRGR2gJW14RKDD0wFL8TT1g= X-ClientProxiedBy: SG2PR01CA0157.apcprd01.prod.exchangelabs.com (2603:1096:4:28::13) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|GVXPR04MB10705:EE_ X-MS-Office365-Filtering-Correlation-Id: fd5ef55a-528c-4836-77f9-08dc795dabd3 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|7416005|1800799015|52116005|376005|921011|38350700005; X-Microsoft-Antispam-Message-Info: =?utf-8?q?UOpdkJcUj8fBe9g+tIuesC1P96bKXLU?= =?utf-8?q?E2B1Qbgt5e4npeq/qzyoyDX6iEGy3Gw4OGJKNocNAb6VXub0YKyWy3BsRmGla2n9U?= =?utf-8?q?2il2CXNyHbX+Tn6UlzTTnDotCWBonDnTPEdcDEpQfldES0SWgLIbBqTNsOTdX/Lsy?= =?utf-8?q?pAAxZSkA8aFNGjqKs+FHb+k0Olp8teGEyHTZCAVxzflgThmgVqIGhe28L88V0mkxa?= =?utf-8?q?ST7MDoNJLebA/tim4Uu0xnuoFEjp/Yjf1FzRep1M8GJhLG5nBHVJVqIIygfRCwRAz?= =?utf-8?q?Re4x+F+r0nIE/Z8QpRwqTYY7fYvr423z+iwDME2cyBiB+HmxhO4AKVbuiwrmLa4K+?= =?utf-8?q?afRyW7AOxEBm0IuudUHR1Olb7v+gSoPFxhH9V7izFO3990RtdGkt6rG73IhLXjhrh?= =?utf-8?q?cvYFMK2IrRnz+n1NCQg6uh4I0TjPghv3u/YCsixhijXKE+cPwQ54enYMVTtRyO4Hl?= =?utf-8?q?U1nJQFe2MBuhzk9LCkhnq0+LKgwK1Yh5rtv5JDAYchMSA5gmMMtTZ9z1UVWul96Hr?= =?utf-8?q?CKzFWnuj83GEoyXxv+boK1xpC+60zwJdlDa+bCOyMjGVNed8vYY0QLA/64G3HGMgU?= =?utf-8?q?ufF8VQ+KpZpKJC6briKXxXQUPPWBI9mHF1BqON9UWdY5X00V5r9UtuIU9/Wge/Pcz?= =?utf-8?q?A0p5lkNTHxdVeExKheM14Fs+ayQz1Hra/UvO8/ufyKYPcfkBMSasPxMq+h3+0zB1D?= =?utf-8?q?O6zBA95bWfkKnJiHV09Xpw0QhInO64M2E0WQSODwJevmoU9g2FIcLeL/C4fHR0By4?= =?utf-8?q?qgNEaHrAI1YpRwhJ334qlkLTigewx1wvH1pcicXoezyZOux496AiZDiityGee5Wn7?= =?utf-8?q?R73pK1lnbURqoIVWncAtcxJ/o1aYzQeaeIelBHZenu9WRkzd9qEyuIc6Fa5Sf4tof?= =?utf-8?q?AHlkIsmirKtoDkmKEZF/C18GDTeJK3F1zWyDd4GGJVt1OgrwzOptKfc2l/zJodq5b?= =?utf-8?q?VsH8I5K580Y6A8AI7SHM1+pJ7py1DfvkeNubSBsw1ItSbL4fz1d6ogcUkVjqdDiw2?= =?utf-8?q?k/lcNB+TD9cu847krYgqJS+6gFHtb+P8ZSEyt9Enb+2K+4jnqAYAPBQIAdCvh0BNS?= =?utf-8?q?2mZso7NHTEC0XorXVc+GrKOx8dNK2Y4wMNItbt0G7DnErOYie+9/JtEoGkzQROCK3?= =?utf-8?q?zWwUCTLvsFqTUkbnuQW3VOrCTYsHPbCKQE/6qf2FqflpotffTDEhZE28NnkX1bj01?= =?utf-8?q?NG5anPkO7nQmQoskgt0WhOhekabwBBf7eiCHElsezmNd7Q82I/pDRqXKs/iLCZBUC?= =?utf-8?q?2NOB6Llv9r5fYqLNVVJW2uyK/qJggUM23EPDYNQDRaydcxvPKnGJndxQ=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9417.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366007)(7416005)(1800799015)(52116005)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?Ee03TGNHVHLakMHyFIAu68QJa9zo?= =?utf-8?q?zFFb8EzPycH1U37Q8dwCRg5BsiitiQRwBeD79Q1lLXgCNsgruc9eGIVk6gV4RL6eO?= =?utf-8?q?gb+y0dNz8jeh2xShpAGe/8fh/VKJRUPPfBet5hMsO51JEtqdkgjkN2QRnZBERbdyB?= =?utf-8?q?ZdUPZIg9ujCdYSAdCmFHReT96ufpCwCjsaCd7XV8GmyLi/ffZUg6F2KIRUr3LYqxW?= =?utf-8?q?ynLE61cCrgQpoVbt3Siera+Qo4Rb20XxbM+CB+yfxtr3fbSfhpays4TEvon2nx7jn?= =?utf-8?q?qAB6tlPSRpnC5fPxcVPK27sWoZzhIZm6iy/gDbAAT/FmpEEYN+khaNyYU+4V0fCS7?= =?utf-8?q?BLowj5U3FrCwbsAqSU5S5DdNFegL3/6skY8h9DgrUCDTcqP4I6mnELXedL/VNpH3k?= =?utf-8?q?i1vkJXnpnS5QdAR1J/0atwhPRj/vcursXt44835AFRvDIt4KHEmDR4dJtBighzl3O?= =?utf-8?q?Zpqn7i3Ym909naD0Frx2u9ZKk9abUXyxHuHRRk1EPWf1xU8D7L/DXvZ0bjcWiaY2y?= =?utf-8?q?FgbyoY3/8AYR91crPqbHhbkhufqUAGxXZyCxby6yCKOjkRnxkgvqwsNOcR2752mGD?= =?utf-8?q?5htKtu+ow9Z6Wd0eDno/BuoHCbxQYT5lOzuwSkRnMnbylISYiHAdWc+vEDNJsCAJr?= =?utf-8?q?r2Drm0X0IT/KQpdBJBA3EUgsEaxN2iYrsr8lLrLLQzniAzXtDer8pot6VlgO8vww1?= =?utf-8?q?nRyK54L0EAn/MmAH0jYpamZu/fgmvW656GfApZ8thji5zCm5Vb6hixQZ74qYeYRQF?= =?utf-8?q?w9C9ycmt/pTAcEosDu98RfQJFlP37CPmiQUGBEc7p/OqcgO14kq3XW7AhQuK1USBU?= =?utf-8?q?Pi7TRkvuf6KfAaQwn7LJzy0OrhFmfpKdA7ns3SNZmM7TVOKy2kDXf6VbUG8ucGN5h?= =?utf-8?q?eX3A1/dNTpGmPMmhBikz1tmjnjoczpWKpfIFEdrvrruu7Y4EZFPiSGNU4W2GKnSzU?= =?utf-8?q?crSmbLqTO4X+4CFG7Kp0yimD3ZY+StF3Drl8FIbO5SthfWc35e/TJHSVKjzA70TZV?= =?utf-8?q?NQHe2560ME2z24uHtCfpgeL4u6xW8+EZnrLxA0h5BhynFpM6+rWSy6BIG/M9Liqpj?= =?utf-8?q?tbJAu/I/tJzP5zCrB01Ee93B2jomt6fxThmP1ZB+XMMYB//RwvZJHuRWgFlTGLmWv?= =?utf-8?q?ripqPdXznsFwuEbTzYwMhibD2ju36Uagh1sJPLw9Yrod8JCPNUjWE2WGEamuAvHWl?= =?utf-8?q?/k9kSmS/0a50kWDeDNsf4nuVUBrOEk3xAgHSTaiD4p5xLM5xw6J3Z4VahAro9hDyp?= =?utf-8?q?dfZ95Apfhki4mQxCC3HJ2A1t9o/bPtK6Cw12NSWMi3f/F3gVgmScd+aw0gk+1mgbe?= =?utf-8?q?TAN9V8RMVUgO9Ilot+VJmUnAiuIFAGM7O67bDGj10wnGlnBABEYfjG6gLFouq7tJL?= =?utf-8?q?CU2DggiC761ASL7ogzxQjLsqYKOD9OmxJDgylwZxs4AWq/+f5pDit+o8vi/DHClEx?= =?utf-8?q?OzmDIepcXM6GnzvI/osuWOipsas8TLYjh45iNhDasDMujui+xJkPs7RnvP0Gw46oy?= =?utf-8?q?Ecnw5RNUm0gj?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: fd5ef55a-528c-4836-77f9-08dc795dabd3 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 06:17:20.2536 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5GlEU/kGWQ8dw1KB/DjBmBphhB/4YcIquLe4d4nOmFNqDk8qP9eO5xcdmHNWTOLcSol383BxaMNm1V1Muusbjg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR04MB10705 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240520_231733_548534_50AE77FB X-CRM114-Status: GOOD ( 18.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Peng Fan The generic pinctrl-scmi.c driver could not be used for i.MX95 because i.MX95 SCMI firmware not supports functions, groups or generic 'Pin Configuration Type and Enumerations' listed in SCMI Specification. i.MX95 System Control Management Interface(SCMI) firmware only supports below pin configuration types which are OEM specific types: 192: PIN MUX 193: PIN CONF 194: DAISY ID 195: DAISY VAL To Support fsl,pins property together with SCMI OEM protocol, add this driver. Signed-off-by: Peng Fan Reviewed-by: Cristian Marussi Acked-by: Sudeep Holla --- drivers/pinctrl/freescale/Kconfig | 9 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx-scmi.c | 357 +++++++++++++++++++++++++++ 3 files changed, 367 insertions(+) diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 27bdc548f3a7..711a5ab3ceb1 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -7,6 +7,15 @@ config PINCTRL_IMX select PINCONF select REGMAP +config PINCTRL_IMX_SCMI + tristate "i.MX95 pinctrl driver using SCMI protocol interface" + depends on ARM_SCMI_PROTOCOL && OF || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + help + i.MX95 SCMI firmware provides pinctrl protocol. This driver + utilizes the SCMI interface to do pinctrl configuration. + config PINCTRL_IMX_SCU tristate depends on IMX_SCU diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 647dff060477..e79b4b06e71b 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -2,6 +2,7 @@ # Freescale pin control drivers obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o +obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-imx-scmi.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c new file mode 100644 index 000000000000..2991047535bc --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Power Interface (SCMI) Protocol based i.MX pinctrl driver + * + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "../pinctrl-utils.h" +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" + +#define DRV_NAME "scmi-pinctrl-imx" + +struct scmi_pinctrl_imx { + struct device *dev; + struct scmi_protocol_handle *ph; + struct pinctrl_dev *pctldev; + struct pinctrl_desc pctl_desc; + const struct scmi_pinctrl_proto_ops *ops; +}; + +/* SCMI pin control types, aligned with SCMI firmware */ +#define IMX_SCMI_NUM_CFG 4 +#define IMX_SCMI_PIN_MUX 192 +#define IMX_SCMI_PIN_CONFIG 193 +#define IMX_SCMI_PIN_DAISY_ID 194 +#define IMX_SCMI_PIN_DAISY_CFG 195 + +#define IMX_SCMI_NO_PAD_CTL BIT(31) +#define IMX_SCMI_PAD_SION BIT(30) +#define IMX_SCMI_IOMUXC_CONFIG_SION BIT(4) + +#define IMX_SCMI_PIN_SIZE 24 + +#define IMX95_DAISY_OFF 0x408 + +static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct pinctrl_map *new_map; + const __be32 *list; + unsigned long *configs = NULL; + unsigned long cfg[IMX_SCMI_NUM_CFG]; + int map_num, size, pin_size, pin_id, num_pins; + int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; + int i, j; + uint32_t ncfg; + static uint32_t daisy_off; + + if (!daisy_off) { + if (of_machine_is_compatible("fsl,imx95")) { + daisy_off = IMX95_DAISY_OFF; + } else { + dev_err(pctldev->dev, "platform not support scmi pinctrl\n"); + return -EINVAL; + } + } + + list = of_get_property(np, "fsl,pins", &size); + if (!list) { + dev_err(pctldev->dev, "no fsl,pins property in node %pOF\n", np); + return -EINVAL; + } + + pin_size = IMX_SCMI_PIN_SIZE; + + if (!size || size % pin_size) { + dev_err(pctldev->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); + return -EINVAL; + } + + num_pins = size / pin_size; + map_num = num_pins; + + new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), + GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map = new_map; + *num_maps = map_num; + + /* create config map */ + for (i = 0; i < num_pins; i++) { + j = 0; + ncfg = IMX_SCMI_NUM_CFG; + mux_reg = be32_to_cpu(*list++); + conf_reg = be32_to_cpu(*list++); + input_reg = be32_to_cpu(*list++); + mux_val = be32_to_cpu(*list++); + input_val = be32_to_cpu(*list++); + conf_val = be32_to_cpu(*list++); + if (conf_val & IMX_SCMI_PAD_SION) + mux_val |= IMX_SCMI_IOMUXC_CONFIG_SION; + + pin_id = mux_reg / 4; + + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val); + + if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL)) + ncfg--; + else + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, conf_val); + + if (!input_reg) { + ncfg -= 2; + } else { + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_ID, + (input_reg - daisy_off) / 4); + cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG, input_val); + } + + configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL); + + new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_id); + new_map[i].data.configs.configs = configs; + new_map[i].data.configs.num_configs = ncfg; + } + + return 0; +} + +static void pinctrl_scmi_imx_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops pinctrl_scmi_imx_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinctrl_scmi_imx_dt_node_to_map, + .dt_free_map = pinctrl_scmi_imx_dt_free_map, +}; + +static int pinctrl_scmi_imx_func_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + /* + * For i.MX SCMI PINCTRL , postpone the mux setting + * until config is set as they can be set together + * in one IPC call + */ + return 0; +} + +static const struct pinmux_ops pinctrl_scmi_imx_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = pinctrl_scmi_imx_func_set_mux, +}; + +static int pinctrl_scmi_imx_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + int ret; + struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev); + u32 config_type, val; + + if (!config) + return -EINVAL; + + config_type = pinconf_to_config_param(*config); + + ret = pmx->ops->settings_get_one(pmx->ph, pin, PIN_TYPE, config_type, &val); + /* Convert SCMI error code to PINCTRL expected error code */ + if (ret == -EOPNOTSUPP) + return -ENOTSUPP; + if (ret) + return ret; + + *config = pinconf_to_config_packed(config_type, val); + + dev_dbg(pmx->dev, "pin:%s, conf:0x%x", pin_get_name(pctldev, pin), val); + + return 0; +} + +static int pinctrl_scmi_imx_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum scmi_pinctrl_conf_type config_type[IMX_SCMI_NUM_CFG]; + u32 config_value[IMX_SCMI_NUM_CFG]; + enum scmi_pinctrl_conf_type *p_config_type = config_type; + u32 *p_config_value = config_value; + int ret; + int i; + + if (!configs || !num_configs) + return -EINVAL; + + if (num_configs > IMX_SCMI_NUM_CFG) { + dev_err(pmx->dev, "num_configs(%d) too large\n", num_configs); + return -EINVAL; + } + + for (i = 0; i < num_configs; i++) { + /* cast to avoid build warning */ + p_config_type[i] = + (enum scmi_pinctrl_conf_type)pinconf_to_config_param(configs[i]); + p_config_value[i] = pinconf_to_config_argument(configs[i]); + + dev_dbg(pmx->dev, "pin: %u, type: %u, val: 0x%x\n", + pin, p_config_type[i], p_config_value[i]); + } + + ret = pmx->ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs, + p_config_type, p_config_value); + if (ret) + dev_err(pmx->dev, "Error set config %d\n", ret); + + return ret; +} + +static void pinctrl_scmi_imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin_id) +{ + unsigned long config = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, 0); + int ret; + + ret = pinctrl_scmi_imx_pinconf_get(pctldev, pin_id, &config); + if (ret) + config = 0; + else + config = pinconf_to_config_argument(config); + + seq_printf(s, "0x%lx", config); +} + +static const struct pinconf_ops pinctrl_scmi_imx_pinconf_ops = { + .pin_config_get = pinctrl_scmi_imx_pinconf_get, + .pin_config_set = pinctrl_scmi_imx_pinconf_set, + .pin_config_dbg_show = pinctrl_scmi_imx_pinconf_dbg_show, +}; + +static int +scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *desc) +{ + struct pinctrl_pin_desc *pins; + unsigned int npins; + int ret, i; + + npins = pmx->ops->count_get(pmx->ph, PIN_TYPE); + pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < npins; i++) { + pins[i].number = i; + /* no need free name, firmware driver handles it */ + ret = pmx->ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name); + if (ret) + return dev_err_probe(pmx->dev, ret, + "Can't get name for pin %d", i); + } + + desc->npins = npins; + desc->pins = pins; + dev_dbg(pmx->dev, "got pins %u", npins); + + return 0; +} + +static const char * const scmi_pinctrl_imx_allowlist[] = { + "fsl,imx95", + NULL +}; + +static int scmi_pinctrl_imx_probe(struct scmi_device *sdev) +{ + struct device *dev = &sdev->dev; + const struct scmi_handle *handle = sdev->handle; + struct scmi_pinctrl_imx *pmx; + struct scmi_protocol_handle *ph; + const struct scmi_pinctrl_proto_ops *pinctrl_ops; + int ret; + + if (!handle) + return -EINVAL; + + if (!of_machine_compatible_match(scmi_pinctrl_imx_allowlist)) + return -ENODEV; + + pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph); + if (IS_ERR(pinctrl_ops)) + return PTR_ERR(pinctrl_ops); + + pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->ph = ph; + pmx->ops = pinctrl_ops; + + pmx->dev = dev; + pmx->pctl_desc.name = DRV_NAME; + pmx->pctl_desc.owner = THIS_MODULE; + pmx->pctl_desc.pctlops = &pinctrl_scmi_imx_pinctrl_ops; + pmx->pctl_desc.pmxops = &pinctrl_scmi_imx_pinmux_ops; + pmx->pctl_desc.confops = &pinctrl_scmi_imx_pinconf_ops; + + ret = scmi_pinctrl_imx_get_pins(pmx, &pmx->pctl_desc); + if (ret) + return ret; + + pmx->dev = &sdev->dev; + + ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx, + &pmx->pctldev); + if (ret) + return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); + + return pinctrl_enable(pmx->pctldev); +} + +static const struct scmi_device_id scmi_id_table[] = { + { SCMI_PROTOCOL_PINCTRL, "pinctrl-imx" }, + { } +}; +MODULE_DEVICE_TABLE(scmi, scmi_id_table); + +static struct scmi_driver scmi_pinctrl_imx_driver = { + .name = DRV_NAME, + .probe = scmi_pinctrl_imx_probe, + .id_table = scmi_id_table, +}; +module_scmi_driver(scmi_pinctrl_imx_driver); + +MODULE_AUTHOR("Peng Fan "); +MODULE_DESCRIPTION("i.MX SCMI pin controller driver"); +MODULE_LICENSE("GPL");