From patchwork Sat Jun 1 12:15:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13682373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA312C27C44 for ; Sat, 1 Jun 2024 12:35:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tHbyFA+1ikcJosUVptoLVauMptNpwIKK+3zVl8dOhQk=; b=2gkkPRMOx61v7W kcn7cqJZXFr1c3tQFxaPIbbueCOgRcc/T5oz5VuuaQGh5rt7MtP+9HU67HpQenYCpgmtWDZcJZZqR I7aCTJus28yQ5UXbIrpiQL8MSmlt+q1uwOK8nPjPS3074NrkBge86n2VpIwvqLKSUSi9X+mReVqxI i20+vSkb+JhAZeKoPnwdlXomyo2crL697yzZ1esYgC1xieP+Czk7f6qv8kwb0/VgbfZaylq+gGIxl obotBwvbMicmNQyKeYt89VEHk5vleEr09HrRP7veL+f6NtdvCG0ge6ZasH//YM5W2aEQ9+wEpdZXY vpoQmAButxpu+csXtfpg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sDNwu-0000000Cb0F-3sLo; Sat, 01 Jun 2024 12:35:04 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sDNeq-0000000CUIp-1eXr for linux-arm-kernel@lists.infradead.org; Sat, 01 Jun 2024 12:16:26 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 451CGMSv024787; Sat, 1 Jun 2024 07:16:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717244182; bh=H04MciwvQkqXdeK3r1sVJaJISF2/zqLrsqaTKdhCOds=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rrG/Jc7WD4KLiIuNT38t87+VAvSfi7WByX3zZrmGwVHTWH8CIGUN3qCT+wCvRwbEO nPt9JKs7nMs+d+jqBpMvf2nvaZ76NXoI3PiGSpWhUOV+iOtGvOYNdNwy4B+XqVD/eY MC+HvHSct4uqZBwDxOrFZ5Lmb4P/ofJqAu+i2VfY= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 451CGLxT001084 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 1 Jun 2024 07:16:22 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 1 Jun 2024 07:16:21 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 1 Jun 2024 07:16:21 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 451CFtkJ009323; Sat, 1 Jun 2024 07:16:17 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v4 5/7] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Date: Sat, 1 Jun 2024 17:45:52 +0530 Message-ID: <20240601121554.2860403-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240601121554.2860403-1-s-vadapalli@ti.com> References: <20240601121554.2860403-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240601_051624_533005_EBFE88A2 X-CRM114-Status: GOOD ( 10.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SERDES0 and SERDES1 instances of SERDES on J722S are single lane SERDES which are individually muxed across different peripherals. LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is muxed between PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli --- v3: https://lore.kernel.org/r/20240524090514.152727-4-s-vadapalli@ti.com/ and https://lore.kernel.org/r/20240524090514.152727-6-s-vadapalli@ti.com/ Changes since v3: - Above changes have been squashed into this patch. arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index a011ad893b44..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,12 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */