| Message ID | 20240601121554.2860403-8-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add PCIe, SERDES and USB DT support for J722S | expand |
On 6/1/24 7:15 AM, Siddharth Vadapalli wrote: > Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0 > of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to > interface with the Type-C port via the USB hub, by configuring the pin P05 > of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed > mode of operation with Lane 0 of the SERDES0 instance of SERDES. > > Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > v3: > https://lore.kernel.org/r/20240524090514.152727-4-s-vadapalli@ti.com/ > and > https://lore.kernel.org/r/20240524090514.152727-8-s-vadapalli@ti.com/ > Changes since v3: > - Above patches have been squashed into this patch. > > arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 72 +++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts > index bf3c246d13d1..3145e680e2d3 100644 > --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts > @@ -9,7 +9,9 @@ > /dts-v1/; > > #include <dt-bindings/net/ti-dp83867.h> > +#include <dt-bindings/phy/phy.h> > #include "k3-j722s.dtsi" > +#include "k3-serdes.h" > > / { > compatible = "ti,j722s-evm", "ti,j722s"; > @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ > J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ > >; > }; > + > + main_usb1_pins_default: main-usb1-default-pins { > + pinctrl-single,pins = < > + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ > + >; > + }; > }; > > &cpsw3g { > @@ -301,6 +309,13 @@ exp1: gpio@23 { > "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", > "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", > "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; > + > + p05-hog { > + /* P05 - USB2.0_MUX_SEL */ > + gpio-hog; > + gpios = <5 GPIO_ACTIVE_HIGH>; > + output-high; > + }; > }; > }; > > @@ -384,3 +399,60 @@ &sdhci1 { > status = "okay"; > bootph-all; > }; > + > +&serdes_ln_ctrl { > + idle-states = <J722S_SERDES0_LANE0_USB>, > + <J722S_SERDES1_LANE0_PCIE0_LANE0>; > +}; > + > +&serdes0 { > + status = "okay"; > + serdes0_usb_link: phy@0 { > + reg = <0>; > + cdns,num-lanes = <1>; > + #phy-cells = <0>; > + cdns,phy-type = <PHY_TYPE_USB3>; > + resets = <&serdes_wiz0 1>; > + }; > +}; > + > +&serdes1 { > + serdes1_pcie_link: phy@0 { > + reg = <0>; > + cdns,num-lanes = <1>; > + #phy-cells = <0>; > + cdns,phy-type = <PHY_TYPE_PCIE>; > + resets = <&serdes_wiz1 1>; > + }; > +}; > + > +&pcie0_rc { > + status = "okay"; As much as I like these at the top, the new format rules seems to suggest "status" properties should go at the bottom of the node. Andrew > + reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; > + phys = <&serdes1_pcie_link>; > + phy-names = "pcie-phy"; > +}; > + > +&usbss0 { > + ti,vbus-divider; > + status = "okay"; > +}; > + > +&usb0 { > + dr_mode = "otg"; > + usb-role-switch; > +}; > + > +&usbss1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_usb1_pins_default>; > + ti,vbus-divider; > + status = "okay"; > +}; > + > +&usb1 { > + dr_mode = "host"; > + maximum-speed = "super-speed"; > + phys = <&serdes0_usb_link>; > + phy-names = "cdns3,usb3-phy"; > +};
On Mon, Jun 03, 2024 at 09:21:11AM -0500, Andrew Davis wrote: > On 6/1/24 7:15 AM, Siddharth Vadapalli wrote: > > Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0 > > of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to > > interface with the Type-C port via the USB hub, by configuring the pin P05 > > of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed [...] > > + > > +&serdes0 { > > + status = "okay"; > > + serdes0_usb_link: phy@0 { > > + reg = <0>; > > + cdns,num-lanes = <1>; > > + #phy-cells = <0>; > > + cdns,phy-type = <PHY_TYPE_USB3>; > > + resets = <&serdes_wiz0 1>; > > + }; > > +}; > > + > > +&serdes1 { > > + serdes1_pcie_link: phy@0 { > > + reg = <0>; > > + cdns,num-lanes = <1>; > > + #phy-cells = <0>; > > + cdns,phy-type = <PHY_TYPE_PCIE>; > > + resets = <&serdes_wiz1 1>; > > + }; > > +}; > > + > > +&pcie0_rc { > > + status = "okay"; > > As much as I like these at the top, the new format rules seems to > suggest "status" properties should go at the bottom of the node. I failed to notice that. Thank you for pointing this out. I will fix this in the v5 series. [...] Regards, Siddharth.
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index bf3c246d13d1..3145e680e2d3 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -9,7 +9,9 @@ /dts-v1/; #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy.h> #include "k3-j722s.dtsi" +#include "k3-serdes.h" / { compatible = "ti,j722s-evm", "ti,j722s"; @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; &cpsw3g { @@ -301,6 +309,13 @@ exp1: gpio@23 { "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + + p05-hog { + /* P05 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; }; }; @@ -384,3 +399,60 @@ &sdhci1 { status = "okay"; bootph-all; }; + +&serdes_ln_ctrl { + idle-states = <J722S_SERDES0_LANE0_USB>, + <J722S_SERDES1_LANE0_PCIE0_LANE0>; +}; + +&serdes0 { + status = "okay"; + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz1 1>; + }; +}; + +&pcie0_rc { + status = "okay"; + reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +};