From patchwork Tue Jun 4 08:52:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13684906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8AC1C25B7E for ; Tue, 4 Jun 2024 08:53:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jtJAL76BQAogDc9RaE/26Rl/PqJGI7kISC+vEF9dUbk=; b=PvldXYShtagMEl vl9mgfLNjc5Oa/HB7XovViV+JRoKPoYIvSHs+tXtSDahn3agENPnCHHgTpyVZPddy2sq5uay/ItZu +pOArypgjw1lTedFtEfKXg30jCl0EgSbB61Gy2P32suqzXRD5dY5iEvIY+1bFlxGSf1B67J1Ff32Y vQWibYmsoNkmbD71dDmy5SC0PO0ld7iqyGALMnQ0whL+BR+l/NGC+0j2dOb0EnGifAgMMDvnklbqi PvKVtoWaOnxyS3cunnf3da0jH2LL8MbARHWil1fX/2blEc3H5FkFTn89oYfiasPzY4OPnkP/flOqW +G0G1+oRloFxXH7BqsBg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEPv2-00000001kKl-2Ysl; Tue, 04 Jun 2024 08:53:24 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEPux-00000001kFe-3Xat for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2024 08:53:21 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4548rF7L069305; Tue, 4 Jun 2024 03:53:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717491195; bh=A3xBNcQ8wLm8339Z6LOc/8zgbSMmT1b2GM+j9FvE9oU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZEVicY3Oo9P/hJok/hGUt9hnn5b/9TsIglsyKb0xhWPF2LQUtWj2q7Xck1ZHFq87j xymCE6AKpRQ6RvHK21E6Ql0FOo9hFs8CC70YQAwFdeT3h4GkE1wcPovE88UzV6JzpR cXjb8Dek8HrDbB4YoGE7SVZXubc2xRva+kA8DFn4= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4548rFxY016073 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2024 03:53:15 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 4 Jun 2024 03:53:15 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 4 Jun 2024 03:53:15 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4548qqQl066926; Tue, 4 Jun 2024 03:53:11 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi Date: Tue, 4 Jun 2024 14:22:49 +0530 Message-ID: <20240604085252.3686037-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240604085252.3686037-1-s-vadapalli@ti.com> References: <20240604085252.3686037-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240604_015320_133687_C2495E7E X-CRM114-Status: GOOD ( 11.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which contains the nodes shared with AM62P, followed by including the J722S specific main domain peripherals contained in "k3-j722s-main.dtsi". Signed-off-by: Siddharth Vadapalli --- v4: https://lore.kernel.org/r/20240601121554.2860403-5-s-vadapalli@ti.com/ No changes since v4. arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index c75744edb143..9e04e6a5c0fd 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -10,12 +10,107 @@ #include #include -#include "k3-am62p5.dtsi" +#include "k3-am62p-j722s-common.dtsi" +#include "k3-j722s-main.dtsi" / { model = "Texas Instruments K3 J722S SoC"; compatible = "ti,j722s"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + cbass_main: bus@f0000 { compatible = "simple-bus"; #address-cells = <2>;