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([110.93.11.116]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35e5bb909d1sm5107822f8f.88.2024.06.04.04.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 04:50:03 -0700 (PDT) From: Krzysztof Kozlowski To: Conor Dooley , Nicolas Ferre , Claudiu Beznea , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] arm64: dts: microchip: sparx5_pcb135: move non-MMIO nodes out of axi Date: Tue, 4 Jun 2024 13:49:49 +0200 Message-ID: <20240604114949.165223-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240604114949.165223-1-krzysztof.kozlowski@linaro.org> References: <20240604114949.165223-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240604_045008_776824_E2215756 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org simple-bus nodes, so the "axi" node, should not have non-MMIO children as pointed out by simple-bus schema dtbs_check: sparx5_pcb135_emmc.dtb: axi@600000000: sfp-eth60: {'compatible': ... should not be valid under {'type': 'object'} from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Reported-by: Rob Herring Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski --- .../dts/microchip/sparx5_pcb135_board.dtsi | 95 +++++++++---------- 1 file changed, 47 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index af2f1831f07f..196868898f49 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -13,6 +13,13 @@ gpio-restart { priority = <200>; }; + i2c0_imux: i2c-mux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + }; + leds { compatible = "gpio-leds"; led-0 { @@ -56,6 +63,46 @@ led-7 { default-state = "off"; }; }; + + sfp_eth60: sfp-eth60 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth61: sfp-eth61 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth62: sfp-eth62 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; + }; + + sfp_eth63: sfp-eth63 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp4>; + tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; + }; }; &gpio { @@ -119,15 +166,6 @@ &sgpio2 { microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; }; -&axi { - i2c0_imux: i2c-mux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; -}; - &i2c0_imux { pinctrl-names = "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4", @@ -159,45 +197,6 @@ i2c_sfp4: i2c@3 { }; }; -&axi { - sfp_eth60: sfp-eth60 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>; - }; - sfp_eth61: sfp-eth61 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>; - }; - sfp_eth62: sfp-eth62 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp3>; - tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>; - }; - sfp_eth63: sfp-eth63 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp4>; - tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>; - rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>; - los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>; - tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>; - }; -}; - &mdio0 { status = "okay"; phy0: ethernet-phy@0 {