From patchwork Wed Jun 5 11:41:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13686728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 093D3C27C53 for ; Wed, 5 Jun 2024 11:50:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2wgfzdJfZ1/E22Nu2rHFQ4T08GD8U7BJ6gOVgz1I5ow=; b=wWvEaxskaT8y5D KqPjDVkjdxNNA+NQV75IUDJXzk7T1w7T/hEUVfn6CUXgOzYIFM6rebwtSDy04KqZTvs7qLxGOqq+W BJXrkoMDMlRYSJKCsfCoGTe/GEfnQzhzRhWIs+bZa/0I2sq2fjpezcNIfYEeIOWikTD3QmRjcZ9tF CshXpizu653yBUfVZhdKF77gf//yw74K/wgdmsXUUlKEGAB466fPRl6Nc0DTaz0oDbtMQT3Z2nEPO J6aTMocPaBWenj02MTXcFZz0gznQFrxgH4woNjQUY601FWdBliK0o7oLUAXzzPCFvDPsPk79gYt9j 62+6Ck9Lwrr8JUpstBNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEp9j-00000005mXX-0coA; Wed, 05 Jun 2024 11:50:15 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEp9e-00000005mUK-3pcu for linux-arm-kernel@lists.infradead.org; Wed, 05 Jun 2024 11:50:12 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 554696181B; Wed, 5 Jun 2024 11:50:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB49BC4AF0A; Wed, 5 Jun 2024 11:50:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717588210; bh=0HRuKE8VlXUba+j3EwHzj90KT4DQxSJsorHaMRo2+XQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JTc6iI5Xt2gKkG6jzOLpgp9JosGSx32VAglx5WX3G2X2sRgBDpIM9ChF7WDq+GHBE cturpVQV9rI/nKk+lShBopKjb0v5c7jNQQg6dxIbtOwJOoFpwsTdJKK4zDXwSi2RYE s7RwqJHwqfFZRqhzLC73vkblm98Xz/h716R6kZBid7jMKLP4LjLOgwz2yd6O61Shq5 3b3ODe5E3QJwAZkDUEL/YgW7C45P8d6OGVZ27cDG0WLUZT+TpXAJvBFO2h5fBdZAyX V6SRCgojTr+9u+C9Rt2EuGDBTpp3Yk65p6TPM9ZhkGb9kf6+Jlb9o9U1IOKlhINLj8 8LAa8X/N9sTWg== From: Mark Brown Date: Wed, 05 Jun 2024 12:41:28 +0100 Subject: [PATCH 2/4] arm64/fpsimd: Discover maximum vector length implemented by any CPU MIME-Version: 1.0 Message-Id: <20240605-kvm-arm64-fix-pkvm-sve-vl-v1-2-680d6b43b4c1@kernel.org> References: <20240605-kvm-arm64-fix-pkvm-sve-vl-v1-0-680d6b43b4c1@kernel.org> In-Reply-To: <20240605-kvm-arm64-fix-pkvm-sve-vl-v1-0-680d6b43b4c1@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, Mark Brown X-Mailer: b4 0.14-dev-d4707 X-Developer-Signature: v=1; a=openpgp-sha256; l=4299; i=broonie@kernel.org; h=from:subject:message-id; bh=0HRuKE8VlXUba+j3EwHzj90KT4DQxSJsorHaMRo2+XQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmYFDniQKKB3lNFxU6WDccvOf/Ww+JlNUgz3udSCRy bnFnw/uJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZmBQ5wAKCRAk1otyXVSH0OqyB/ wNfv5HhFD0WNmHYdHM/Rb5yPlCnrAftBkUrzdEtnR5ro/4hHSlplNLYs57As2SqP7e8hwPe0TYSYFk DhvCSELsGfkDFn7PYz+os1aOPgFGHO0SVZ/pJuFLC/ZqI9argK5wg7VoQHZUP9yAy7N3ji7kC5KxLr 8iEa8CzZaIdaMX90p0o4RMO2D7kwv0A0k5VLLaQHZDEUGbbJARn+KBR+huwM3AFw0dvSYc+VkHCc23 po3tNZVqfEeB3xHfXKK2OMkY+NDfGRbSX24mznjzplDD1VlVAFO3O28BAe6S+zYU3o0BBPituikoEH Ae+vh9utlClmvraRzvOBzvbt361e0i X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240605_045011_090814_75937120 X-CRM114-Status: GOOD ( 18.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When discovering the vector lengths for SVE and SME we do not currently record the maximum VL supported on any individual CPU. This is expected to be the same for all CPUs but the architecture allows asymmetry, if we do encounter an asymmetric system then some CPUs may support VLs higher than the maximum Linux will use. Since the pKVM hypervisor needs to support saving and restoring anything the host can physically set it needs to know the maximum value any CPU could have, add support for enumerating it and validation for late CPUs. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 13 +++++++++++++ arch/arm64/kernel/fpsimd.c | 26 +++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 51c21265b4fa..cd19713c9deb 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -188,6 +188,9 @@ struct vl_info { int max_vl; int max_virtualisable_vl; + /* Maximum vector length observed on any CPU */ + int max_cpu_vl; + /* * Set of available vector lengths, * where length vq encoded as bit __vq_to_bit(vq): @@ -278,6 +281,11 @@ static inline int vec_max_virtualisable_vl(enum vec_type type) return vl_info[type].max_virtualisable_vl; } +static inline int vec_max_cpu_vl(enum vec_type type) +{ + return vl_info[type].max_cpu_vl; +} + static inline int sve_max_vl(void) { return vec_max_vl(ARM64_VEC_SVE); @@ -288,6 +296,11 @@ static inline int sve_max_virtualisable_vl(void) return vec_max_virtualisable_vl(ARM64_VEC_SVE); } +static inline int sve_max_cpu_vl(void) +{ + return vec_max_cpu_vl(ARM64_VEC_SVE); +} + /* Ensure vq >= SVE_VQ_MIN && vq <= SVE_VQ_MAX before calling this function */ static inline bool vq_available(enum vec_type type, unsigned int vq) { diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 22542fb81812..27f3593547f1 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -129,6 +129,7 @@ __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = { .min_vl = SVE_VL_MIN, .max_vl = SVE_VL_MIN, .max_virtualisable_vl = SVE_VL_MIN, + .max_cpu_vl = SVE_VL_MIN, }, #endif #ifdef CONFIG_ARM64_SME @@ -1041,8 +1042,13 @@ static void vec_probe_vqs(struct vl_info *info, void __init vec_init_vq_map(enum vec_type type) { struct vl_info *info = &vl_info[type]; + unsigned long b; + vec_probe_vqs(info, info->vq_map); bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX); + + b = find_first_bit(info->vq_map, SVE_VQ_MAX); + info->max_cpu_vl = __bit_to_vl(b); } /* @@ -1054,11 +1060,16 @@ void vec_update_vq_map(enum vec_type type) { struct vl_info *info = &vl_info[type]; DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); + unsigned long b; vec_probe_vqs(info, tmp_map); bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX); bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map, SVE_VQ_MAX); + + b = find_first_bit(tmp_map, SVE_VQ_MAX); + if (__bit_to_vl(b) > info->max_cpu_vl) + info->max_cpu_vl = __bit_to_vl(b); } /* @@ -1069,9 +1080,10 @@ int vec_verify_vq_map(enum vec_type type) { struct vl_info *info = &vl_info[type]; DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); - unsigned long b; + unsigned long b, max_vl; vec_probe_vqs(info, tmp_map); + max_vl = __bit_to_vl(find_first_bit(tmp_map, SVE_VQ_MAX)); bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) { @@ -1083,6 +1095,18 @@ int vec_verify_vq_map(enum vec_type type) if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) return 0; + /* + * pKVM allocates and uses storage for host state based on the + * largest per-PE VL, reject new PEs with a larger maximum. + */ + if (is_protected_kvm_enabled()) { + if (max_vl > info->max_cpu_vl) { + pr_warn("%s: cpu%d: would increase maximum VL\n", + info->name, smp_processor_id()); + return -EINVAL; + } + } + /* * For KVM, it is necessary to ensure that this CPU doesn't * support any vector length that guests may have probed as