From patchwork Wed Jun 5 09:29:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steven Price X-Patchwork-Id: 13686486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 344C4C27C52 for ; Wed, 5 Jun 2024 09:31:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=poZ2LXgZsoExPepXF9NSYLX4LRGkm8OiTxmVNCBSliY=; b=zi6jOI6T9ZMV26 bOcA8uoKpjPIDJH/cI8hD6q8XIYesBHuQMh9e3+IVGruSYjTZaem7m+e6NGKFQloPzbuLtwGhnNh8 GxOVPYZMBi/+goa3MOlXN6lMyWybgDtUnK9pwtAiBDbxqre9gQ5CRz2ggZk4O9erzj4f+t3RbNACb UbmJYgYM06kiYZkqRKB5GySXNe0+nCTE1tZo4Y3PKk4plpRB+9akAJe5X7CcutVxkuXl0tsTyK91B rEnZlhFS9+wDhARC+1LnuqtOm9la3na2ZI6KkuzoCjKLpC+C1daCm1mz7ykg0oAvh3/LtF/Llnm9b lZA2mCHM9bnwdC2Cq8Ug==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEmyx-00000005P4P-3Is8; Wed, 05 Jun 2024 09:30:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEmym-00000005Osq-05H1 for linux-arm-kernel@lists.infradead.org; Wed, 05 Jun 2024 09:30:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDF28DA7; Wed, 5 Jun 2024 02:31:11 -0700 (PDT) Received: from e122027.arm.com (unknown [10.57.39.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A78B3F792; Wed, 5 Jun 2024 02:30:44 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni Subject: [PATCH v3 07/14] arm64: Make the PHYS_MASK_SHIFT dynamic Date: Wed, 5 Jun 2024 10:29:59 +0100 Message-Id: <20240605093006.145492-8-steven.price@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605093006.145492-1-steven.price@arm.com> References: <20240605093006.145492-1-steven.price@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240605_023048_354945_F7DB229D X-CRM114-Status: GOOD ( 11.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Make the PHYS_MASK_SHIFT dynamic for Realms. This is only is required for masking the PFN from a pte entry. For a realm phys_mask_shift is reduced if the RMM reports a smaller configured size for the guest. Co-developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price --- v3: Drop the MAX_PHYS_MASK{,_SHIFT} definitions as they are no longer needed. --- arch/arm64/include/asm/pgtable-hwdef.h | 6 ------ arch/arm64/include/asm/pgtable.h | 5 +++++ arch/arm64/kernel/rsi.c | 5 +++++ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 9943ff0af4c9..2e3af0693bd8 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -203,12 +203,6 @@ */ #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) -/* - * Highest possible physical address supported. - */ -#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) - #define TTBR_CNP_BIT (UL(1) << 0) /* diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index f8efbc128446..11d614d83317 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -39,6 +39,11 @@ #include #include +extern unsigned int phys_mask_shift; + +#define PHYS_MASK_SHIFT (phys_mask_shift) +#define PHYS_MASK ((1UL << PHYS_MASK_SHIFT) - 1) + #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE diff --git a/arch/arm64/kernel/rsi.c b/arch/arm64/kernel/rsi.c index d34e05b339ae..c5c03e8e341a 100644 --- a/arch/arm64/kernel/rsi.c +++ b/arch/arm64/kernel/rsi.c @@ -12,6 +12,8 @@ struct realm_config config; unsigned long prot_ns_shared; EXPORT_SYMBOL(prot_ns_shared); +unsigned int phys_mask_shift = CONFIG_ARM64_PA_BITS; + DEFINE_STATIC_KEY_FALSE_RO(rsi_present); EXPORT_SYMBOL(rsi_present); @@ -72,6 +74,9 @@ void __init arm64_rsi_init(void) return; prot_ns_shared = BIT(config.ipa_bits - 1); + if (config.ipa_bits - 1 < phys_mask_shift) + phys_mask_shift = config.ipa_bits - 1; + static_branch_enable(&rsi_present); }