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Wysocki" , Viresh Kumar , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo CC: Vibhore Vardhan , , , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3899; i=bb@ti.com; h=from:subject:message-id; bh=bsU/uSufwYkHHioRdRIW2VKG45iABEGGxk+o7JmN7xk=; b=owNCWmg5MUFZJlNZkMuWPAAAXf///r99v7uzvPbvy2sr23/39rlybIbL+9/vfH//7jf9/8ywA RswIeoGho0A0AAaNogaBkDQA0DQ0GjTQDQaDQAaMgGjQDIA00aDI2hG1NG0ynpEDI0A0BoGjCDJ oNA9BDJk00AwIBoZDIA2oAaZMmmhoGmTQBo0ZBo0AZBkyHTTaIZMg0aNGRkGI0yaGhkZAyaAwQA 0Bo0D1AGRiAAyaNGjQNMmgyGhiAAAAHUJUh78MLEjC9iSD/ag2iEzqAbDBC/QElAoOZIAkex3Wv 5wCAhyRmodIv2wl0EFESd+TL02k/Zl2fR6ED7FodS8z3yDJKH4bepxRobu/4NMDXII+HL97oGZT HYnlBdHo7+CHMcXNSOtYuqiQzlwgBGyoOvgsuMBTq/s/Z+durXJq9soyczkpICtAFvvP+0GChfM opymdiJoNbDMTYSU+cTON1IWthFywI12HBBV6O1Utk90tSTDLP9VK3kLdsp0DGI5MIViADAYIiC teHBQVosC1kB0HbbpFcKuoB1Bl8hJFce8kzdU1LlGDMjiFGm57khGAyEuydGJtmyMnm4BW8+kJ0 MP9QAY6VP3/KMEeX4z4zq25SR8YuAIisXfuHHjQX3iuRhyITjpFFIVXMQpyakapVT6seAaq3Ic2 oA2bByT+0Tkt/i7kinChISGXLHg X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240612_094216_830140_7FD7D6FD X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To help reduce power consumption, reduce the frequency of the CPU cores when they sit idle by specifying their supported OPP entries. Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 6 ++++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 ++++++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 +++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi index c71d9624ea277..8392c8cde2cd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -19,6 +19,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + usb0_phy_ctrl: syscon@4008 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4008 0x4>; @@ -28,6 +33,7 @@ usb1_phy_ctrl: syscon@4018 { compatible = "ti,am62-usb-phy-ctrl", "syscon"; reg = <0x4018 0x4>; }; + }; wkup_uart0: serial@2b300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 6983ec1b57cbd..08956ac1eaead 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi index 41f479dca4555..140587d02e88e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; }; @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; }; @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; }; @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible = "cache"; cache-unified;