From patchwork Sat Jun 15 08:15:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FAF4C27C53 for ; Sat, 15 Jun 2024 08:16:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ToP5EKkVGa1u0JhGEFQvR0WDOaWbVtUSajWl2oNi+AY=; b=PDqPbouxdvEJcsA4yEY/EEYmlp eSMxKs53KeHKN2zcxgc8LjV5HF8uVfo8rVhbG+9rHvUzZ2n6R/VQf4BRJMm/9H7XM0tIYbhn9Yoil zCQCBFL95RSFEn5G+zmwZ1KUrryCJUns76gW342APYmCgW8fYd38p4VhSJuLbwS/eiwRwxyioS9qi UwQI2lWv8wXmPOM5R/xA3j/NLto26MdGV4amlVDyh/oUnTEedLeWv0m+/ZfMhXpXD1gz8wHuGFBja imZqvajgLtHUzsgRRczUVLjSVNI1rNi4wqxRIe2fC5ano2DZlk/v1syVrYMhgB2bqRp0itP6gMg6R MVANj4NA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOab-00000004zD9-0rx1; Sat, 15 Jun 2024 08:16:45 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaT-00000004z7L-0dYI for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:38 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GSPU102747; Sat, 15 Jun 2024 03:16:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439388; bh=ToP5EKkVGa1u0JhGEFQvR0WDOaWbVtUSajWl2oNi+AY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lnqYIkkCZ2qbWhWBtGWK8YtyvYuNl0AKhwbVx+PKwMntSU7fw1LMi0S/UqgI2YrBA KVB+ap587R+rZnndBv0UzjglzkQUbeifBBHgbmR8Grbpm/COGnmv/K4W8O+LNj30wZ uAlsi5Z0+pxU3OgEat5+6+BJZOCd2sFJz1uxSTo8= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GSvm084490 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:28 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:27 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:27 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1QZ024463; Sat, 15 Jun 2024 03:16:23 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 5/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Date: Sat, 15 Jun 2024 13:45:57 +0530 Message-ID: <20240615081600.3602462-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011637_338737_39798902 X-CRM114-Status: UNSURE ( 9.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SERDES0 and SERDES1 instances of SERDES on J722S are single lane SERDES which are individually muxed across different peripherals. LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is muxed between PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-7-s-vadapalli@ti.com/ No changes since v6. arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index a011ad893b44..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,12 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */