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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id af79cd13be357-798aaecc004sm432892285a.31.2024.06.17.06.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 06:50:16 -0700 (PDT) From: Trevor Gamblin Date: Mon, 17 Jun 2024 09:49:55 -0400 Subject: [PATCH v3 15/41] iio: adc: qcom-spmi-rradc: make use of regmap_clear_bits(), regmap_set_bits() MIME-Version: 1.0 Message-Id: <20240617-review-v3-15-88d1338c4cca@baylibre.com> References: <20240617-review-v3-0-88d1338c4cca@baylibre.com> In-Reply-To: <20240617-review-v3-0-88d1338c4cca@baylibre.com> To: Jonathan Cameron , Lars-Peter Clausen , Dmitry Rokosov , Michael Hennerich , Cosmin Tanislav , Chen-Yu Tsai , Hans de Goede , Ray Jui , Scott Branden , Broadcom internal kernel review list , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Saravanan Sekar , Orson Zhai , Baolin Wang , Chunyan Zhang , Maxime Coquelin , Alexandre Torgue , =?utf-8?q?Nuno_S=C3=A1?= , Linus Walleij , Jean-Baptiste Maneyrol , Crt Mori Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Trevor Gamblin X-Mailer: b4 0.13.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_065018_797230_B861EB02 X-CRM114-Status: GOOD ( 12.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Instead of using regmap_update_bits() and passing the mask twice, use regmap_set_bits(). Instead of using regmap_update_bits() and passing val = 0, use regmap_clear_bits(). Suggested-by: Uwe Kleine-König Signed-off-by: Trevor Gamblin --- drivers/iio/adc/qcom-spmi-rradc.c | 50 +++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-rradc.c b/drivers/iio/adc/qcom-spmi-rradc.c index 56a713766954..1402df68dd52 100644 --- a/drivers/iio/adc/qcom-spmi-rradc.c +++ b/drivers/iio/adc/qcom-spmi-rradc.c @@ -358,15 +358,15 @@ static int rradc_enable_continuous_mode(struct rradc_chip *chip) int ret; /* Clear channel log */ - ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, - RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL); + ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL); if (ret < 0) { dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); return ret; } - ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG, - RR_ADC_LOG_CLR_CTRL, 0); + ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_LOG, + RR_ADC_LOG_CLR_CTRL); if (ret < 0) { dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", ret); @@ -374,9 +374,8 @@ static int rradc_enable_continuous_mode(struct rradc_chip *chip) } /* Switch to continuous mode */ - ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, - RR_ADC_CTL_CONTINUOUS_SEL, - RR_ADC_CTL_CONTINUOUS_SEL); + ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL); if (ret < 0) dev_err(chip->dev, "Update to continuous mode failed:%d\n", ret); @@ -389,8 +388,8 @@ static int rradc_disable_continuous_mode(struct rradc_chip *chip) int ret; /* Switch to non continuous mode */ - ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL, - RR_ADC_CTL_CONTINUOUS_SEL, 0); + ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_CTL, + RR_ADC_CTL_CONTINUOUS_SEL); if (ret < 0) dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", ret); @@ -434,8 +433,8 @@ static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, return -EINVAL; } - ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, - chan->trigger_mask, chan->trigger_mask); + ret = regmap_set_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask); if (ret < 0) { dev_err(chip->dev, "Failed to apply trigger for channel '%s' ret=%d\n", @@ -469,8 +468,8 @@ static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, rradc_disable_continuous_mode(chip); disable_trigger: - regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr, - chan->trigger_mask, 0); + regmap_clear_bits(chip->regmap, chip->base + chan->trigger_addr, + chan->trigger_mask); return ret; } @@ -481,17 +480,16 @@ static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, { int ret; - ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, - RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, - RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); + ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); if (ret < 0) { dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); return ret; } - ret = regmap_update_bits(chip->regmap, - chip->base + RR_ADC_BATT_ID_TRIGGER, - RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL); + ret = regmap_set_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL); if (ret < 0) { dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); goto out_disable_batt_id; @@ -500,12 +498,12 @@ static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, ret = rradc_read_status_in_cont_mode(chip, chan_address); /* Reset registers back to default values */ - regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, - RR_ADC_TRIGGER_CTL, 0); + regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, + RR_ADC_TRIGGER_CTL); out_disable_batt_id: - regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, - RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0); + regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, + RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); return ret; } @@ -965,9 +963,9 @@ static int rradc_probe(struct platform_device *pdev) if (batt_id_delay >= 0) { batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay); - ret = regmap_update_bits(chip->regmap, - chip->base + RR_ADC_BATT_ID_CFG, - batt_id_delay, batt_id_delay); + ret = regmap_set_bits(chip->regmap, + chip->base + RR_ADC_BATT_ID_CFG, + batt_id_delay); if (ret < 0) { dev_err(chip->dev, "BATT_ID settling time config failed:%d\n",