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AJvYcCWnFgkN76qn5Uzi7KeTFhlauTanXtGSIwPpfyjQSxISorQnNMSlWE2oLsxVRgJIwNQgXVINrT9WgyQfmbSzND8AMPHYpNqf4M7koW8Jf5BgjimPfug= X-Gm-Message-State: AOJu0YzX/kk9QzC2r9/qbl2X1lnDwtmgCKcZs/XqUgiyHh5SA3Cks3XT a1+FDh8WNwvK3vZ2Ko5unuT4qZxIPN1WYgUzx1HCExLAGjHnsqTrp+PcbF5CWqw= X-Google-Smtp-Source: AGHT+IGfQPJkGUEmf7bvL5EHIQMFh2lzC9gdoJFes+mvAbebBn2gmOigq0ygMHUP4CBQUyY/zDxPJA== X-Received: by 2002:a05:6820:80c:b0:5ba:f20c:361b with SMTP id 006d021491bc7-5bdadc84948mr13508706eaf.8.1718671066504; Mon, 17 Jun 2024 17:37:46 -0700 (PDT) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5bd5f2a1801sm1216364eaf.37.2024.06.17.17.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 17:37:46 -0700 (PDT) From: Sam Protsenko To: =?utf-8?q?=C5=81ukasz_Stelmach?= , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Olivia Mackall , Herbert Xu , Alim Akhtar , linux-samsung-soc@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] hwrng: exynos: Implement bus clock control Date: Mon, 17 Jun 2024 19:37:40 -0500 Message-Id: <20240618003743.2975-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240618003743.2975-1-semen.protsenko@linaro.org> References: <20240618003743.2975-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_173747_809641_43FCA4E2 X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some SoCs like Exynos850 might require the SSS bus clock (PCLK) to be enabled in order to access TRNG registers. Add and handle optional PCLK clock accordingly to make it possible. Signed-off-by: Sam Protsenko --- drivers/char/hw_random/exynos-trng.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c index 88a5088ed34d..4520a280134c 100644 --- a/drivers/char/hw_random/exynos-trng.c +++ b/drivers/char/hw_random/exynos-trng.c @@ -47,7 +47,8 @@ struct exynos_trng_dev { struct device *dev; void __iomem *mem; - struct clk *clk; + struct clk *clk; /* operating clock */ + struct clk *pclk; /* bus clock */ struct hwrng rng; }; @@ -141,10 +142,23 @@ static int exynos_trng_probe(struct platform_device *pdev) goto err_clock; } + trng->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); + if (IS_ERR(trng->pclk)) { + ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->pclk), + "cannot get pclk"); + goto err_clock; + } + + ret = clk_prepare_enable(trng->pclk); + if (ret) { + dev_err(&pdev->dev, "Could not enable the pclk.\n"); + goto err_clock; + } + ret = clk_prepare_enable(trng->clk); if (ret) { dev_err(&pdev->dev, "Could not enable the clk.\n"); - goto err_clock; + goto err_clock_enable; } ret = devm_hwrng_register(&pdev->dev, &trng->rng); @@ -160,6 +174,9 @@ static int exynos_trng_probe(struct platform_device *pdev) err_register: clk_disable_unprepare(trng->clk); +err_clock_enable: + clk_disable_unprepare(trng->pclk); + err_clock: pm_runtime_put_noidle(&pdev->dev); @@ -174,6 +191,7 @@ static void exynos_trng_remove(struct platform_device *pdev) struct exynos_trng_dev *trng = platform_get_drvdata(pdev); clk_disable_unprepare(trng->clk); + clk_disable_unprepare(trng->pclk); pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev);