From patchwork Sun Jun 23 13:34:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 13708615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB96AC27C4F for ; Sun, 23 Jun 2024 13:35:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7eKBfK4yQoseJ4UUykQiALl6ktSJlnnFmpnqKIohudk=; b=ELnkuVgUs65HexDFdfMWeiz6L1 0y52/rE7j2kBnRJWSn5CIAhOh15ptl2R0VnJVeUz9/5nPnxQHUpUdoQLW1ybV01pXO/J7xkrzcrDP W3bCunCiU9NxGU6va5aXvnkIR7vLthWhP+ymLRXLjg8alzpskyF8c7qoESK3DvZSG4y7CCdJngfYD VpjvZ1LPs88g6CaiiD0t4Dep5/+MlCGKU/+naReColI3AaN3cMAYpdArtXWHC7la9dqFIKlYQc0m6 9bpNdeFQDX7iHvvwW6VmbWpJ15uajoUZXYpsg3lPtceaGBMFhSJ+AzuL31hypnXLtNM/alHvD9P9a bzbS65eA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLNN2-0000000E4JV-19lN; Sun, 23 Jun 2024 13:35:04 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLNMv-0000000E4Gm-47b7 for linux-arm-kernel@lists.infradead.org; Sun, 23 Jun 2024 13:35:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 49315FEC; Sun, 23 Jun 2024 06:35:20 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 847F63F64C; Sun, 23 Jun 2024 06:34:52 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , James Clark , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Ian Rogers , Mark Rutland , Alexander Shishkin , Adrian Hunter , "Liang, Kan" , Kajol Jain , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 1/2] perf arm-spe: Support multiple Arm SPE PMUs Date: Sun, 23 Jun 2024 14:34:36 +0100 Message-Id: <20240623133437.222736-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240623133437.222736-1-leo.yan@arm.com> References: <20240623133437.222736-1-leo.yan@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240623_063458_100423_0B17A95B X-CRM114-Status: GOOD ( 12.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A platform can have more than one Arm SPE PMU. For example, a system with multiple clusters may have each cluster enabled with its own Arm SPE instance. In such case, the PMU devices will be named 'arm_spe_0', 'arm_spe_1', and so on. Currently, the tool only supports 'arm_spe_0'. This commit extends support to multiple Arm SPE PMUs by detecting the substring 'arm_spe'. Signed-off-by: Leo Yan --- tools/perf/arch/arm/util/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c index 8b7cb68ba1a8..29cfa1e427ed 100644 --- a/tools/perf/arch/arm/util/pmu.c +++ b/tools/perf/arch/arm/util/pmu.c @@ -27,7 +27,7 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) pmu->selectable = true; pmu->is_uncore = false; pmu->perf_event_attr_init_default = arm_spe_pmu_default_config; - if (!strcmp(pmu->name, "arm_spe_0")) + if (strstr(pmu->name, "arm_spe")) pmu->mem_events = perf_mem_events_arm; } else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) { pmu->selectable = true;