From patchwork Mon Jun 24 09:57:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 13709278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D4FAC2BD09 for ; Mon, 24 Jun 2024 10:07:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=0iNOqC4ExHJI9vE+qU5diPKgNqr+3Qv/k5yPv1/9KZw=; b=m89p0i3P0D1onnfgYVqdKlZy4p AKOhNyG7NmCzM+NbhP386ppt/CRuFJmCFECZbo4lOodO4xD+DVTvRf1I3jXq3O5xB4amaX87OYhV5 Zvji0Vr5Yo/W2+cir9ZrzJEzd8qkY6NAV3+eu/cVVOS0M9tj9Re2+RU3ppbHLX94otm2QQ/w2s8Zf 03a7gH7wAJD6pjl3BmkPeIW5NT9OBm3XBsenc0H25OatFXElGPEYIAXeU5cTatkkGayUDtRawjwEe gdH5/P/BBG6dcwpDux0tq9hVYHVSGlG/p6u37hE2pUwwqCbBFv98r4kxEv9SZ8CpKy4RFV9VV2Gsz 3bFgsYQw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLgbu-0000000GMwM-31bd; Mon, 24 Jun 2024 10:07:42 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sLgbo-0000000GMtE-1KAe; Mon, 24 Jun 2024 10:07:38 +0000 X-UUID: 912aecd2321111efb2966dae1f787272-20240624 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=0iNOqC4ExHJI9vE+qU5diPKgNqr+3Qv/k5yPv1/9KZw=; b=JytlDlBLXKeRQXA6lpSpyKVqHCyEiRfrTy0/rZ/LjsohoxxeehLBrpgoE1DGiZOLP/HTZafzRvi5vzSMKRdqyNI8W3NLhOq0RuW7nqO+mtZpgtWg5anCRpcowMHwbPMYOXYCTUCtsA2ZaLbFLVzqFv+hQZ55k8YeR7Ym+QjfZ1E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:919c01be-a291-4b90-94ea-a838d5e7a319,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:393d96e,CLOUDID:5475f688-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 912aecd2321111efb2966dae1f787272-20240624 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1988732566; Mon, 24 Jun 2024 03:07:30 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 24 Jun 2024 17:57:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 24 Jun 2024 17:57:26 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , AngeloGioacchino Del Regno CC: , , , , Jason-ch Chen , "Jason-JH . Lin" , Singo Chang , Nancy Lin Subject: [PATCH] drm/mediatek: Fix bit depth overwritten for mtk_ovl_set bit_depth() Date: Mon, 24 Jun 2024 17:57:26 +0800 Message-ID: <20240624095726.18818-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240624_030736_412825_27E7F36E X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Refine the value and mask define of bit depth for mtk_ovl_set bit_depth(). Use cmdq_pkt_write_mask() instead of cmdq_pkt_write() to avoid bit depth settings being overwritten. Fixes: fb36c5020c9c ("drm/mediatek: Add support for AR30 and BA30 overlays") Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno --- Based on: https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 4b370bc0746d..d35f5b4b22c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -42,7 +42,11 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 -#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 +#define DISP_REG_OVL_CLRFMT_EXT 0x02d0 +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(n) (GENMASK(1, 0) << (4 * (n))) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, n) ((depth) << (4 * (n))) +#define OVL_CON_CLRFMT_8_BIT (0) +#define OVL_CON_CLRFMT_10_BIT (1) #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -65,10 +69,6 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) -#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) -#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) -#define OVL_CON_CLRFMT_8_BIT 0x00 -#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -273,22 +273,17 @@ static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); - unsigned int reg; unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; if (!ovl->data->supports_clrfmt_ext) return; - reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); - reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); - if (is_10bit_rgb(format)) bit_depth = OVL_CON_CLRFMT_10_BIT; - reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); - - mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, - ovl->regs, DISP_REG_OVL_CLRFMT_EXT); + mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx), + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT, + OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx)); } void mtk_ovl_config(struct device *dev, unsigned int w,