From patchwork Tue Jun 25 21:32:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Rapha=C3=ABl_Gallais-Pou?= X-Patchwork-Id: 13712071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08523C30659 for ; Tue, 25 Jun 2024 21:33:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VUkVIkbscryFzLdHAGkO+1ya2/2312ktRzQgqWxaXtI=; b=ItdQW+qaSe5FXq815QN/WFb0un HNtEEYYwxacoBNK2BtICIKmmFVkrGnudheeQsj0+KPQid9c3ke9IqRDBqJn20i7dKSXDNXunfcpfs 5a6tW/8YTUeHPcJA6VG8/fiSj57YThHSPBIcpXTSP4W4FLVYw237e44WVo0S4qEnaVFfZGhew8HDT r6PTtfp3gaGEp+6QgmPgp/J4bkgONQOoKW2m0WZ1DzCWaEmOTYJoxvh1cNtvlQHZUaE9gx+UAWz5O zVn4c/saZRmT73vaigBllSjNBwyE9trrcXlAnJ/ZwiTGLiF1o5CenhxJ+xJs193zxF5xj81P8jowV KIjR9Qfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMDnD-00000004aGC-1Av1; Tue, 25 Jun 2024 21:33:35 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMDmv-00000004aAr-3qUV for linux-arm-kernel@lists.infradead.org; Tue, 25 Jun 2024 21:33:19 +0000 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-362b32fbb3bso3893677f8f.2 for ; Tue, 25 Jun 2024 14:33:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719351196; x=1719955996; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VUkVIkbscryFzLdHAGkO+1ya2/2312ktRzQgqWxaXtI=; b=AS/JffAQHRoPGMv1Y4qs1guRN1ltlRtF88hw0c4DKhmHMvDdBaSO8csDi92ASxAL5U eD6XA4DU6UNkstFtT3IMGXEXAlvJl+fz5m/XCCP5/dqEivMQ211Onfx5WRUpEKEj0Xm8 uxdXFT39UQ8/FtarllvI1qxYmzwrqxKhXn2p3RNEOw3gN2ThT40rOnnNPDizDhVrRYpv ub07mkG96bzppDu6t0L1eqhMz77eJ2FKW/zA70Q7B8wlE2iqv+lQB9nD+NCHOI7KvOJm 70ytRlFIFbDnklVd+erflP/oLUDCt0ACZjypdLer2jXHD2aRW9mARc9NqFhQJaqfke65 T+iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719351196; x=1719955996; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VUkVIkbscryFzLdHAGkO+1ya2/2312ktRzQgqWxaXtI=; b=a0f1Z1aneQJl834MF7UGp9MXd5sgc9srolyqVoBKPmfPAX30ipl2y2oSZ3Jv6bdlCz 7+ZpNYToxnU0lmMK41exGWZ4VNhJA+eyozKmwVB//vfNHK6x0RlT6OW30sf89KCfEyNn j/4rRZK+OsORErG3k8+PzWyM8/mBUcn7KM4h6EsekVshfsoOEh4eyazymBrd32uXe0pS lU3OHxmy89nDt9VhlHhV0GF3Nvb+ICwsod3SsuizXAwPdh5aG0Ef2DVV1ut9bsvRc+4Y r4uPky8dxSTvB1TQ0zUVNZxvcrkx0Zk2RFLEXcPDeaUh1zzwP93UyrgywJpedZ9Bh0C1 Ag0w== X-Forwarded-Encrypted: i=1; AJvYcCWpcdcjtKWtn8hFDgkvl4ti/MSapMMxrnRiDTnQbEtXv46QbRT8s8jxTPuRV5LfaQ4FiItvTDZzb4WqxnD+Kb903B6VgesqB3u4IJQedtD2uY3KxE8= X-Gm-Message-State: AOJu0YxOtcjlglqYnIwDs5ioCf7yTL2PSTICbdylcBF0iOVHbQ0dZQ31 XUsD5NRhHCTc4n9xQp0SH95vI8P6Xkr9Fg4qB26dPokKPxSV8YQ1 X-Google-Smtp-Source: AGHT+IF1vNOVtlSl9cFErkZZ3gZeIrjKfVDkNDpF40NXHmyTCzK4OuWl8NqNcyOSM/LpMW3SCCIssA== X-Received: by 2002:adf:fa4c:0:b0:35d:c106:2db8 with SMTP id ffacd0b85a97d-366e7a63802mr7040004f8f.57.1719351195202; Tue, 25 Jun 2024 14:33:15 -0700 (PDT) Received: from localhost ([2001:861:3385:e20:6384:4cf:52c5:3194]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36647e7eb4fsm13959262f8f.18.2024.06.25.14.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 14:33:15 -0700 (PDT) From: Raphael Gallais-Pou Date: Tue, 25 Jun 2024 23:32:42 +0200 Subject: [PATCH v2 3/3] ARM: dts: sti: add thermal-zones support on stih418 MIME-Version: 1.0 Message-Id: <20240625-thermal-v2-3-bf8354ed51ee@gmail.com> References: <20240625-thermal-v2-0-bf8354ed51ee@gmail.com> In-Reply-To: <20240625-thermal-v2-0-bf8354ed51ee@gmail.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Maxime Coquelin , Alexandre Torgue , Patrice Chotard , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240625_143317_992261_4C7BEFD4 X-CRM114-Status: GOOD ( 16.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a 'thermal-zones' node for stih418. A thermal-zone needs three components: - thermal sensors, described in an earlier commit[1] - cooling devices, specified for each CPU - a thermal zone, describing the overall behavior. The thermal zone needs references to both CPUs and thermal sensors, which phandle are also added. The thermal management will then be achieved on CPUs using the cpufreq framework. [1] https://lore.kernel.org/lkml/20240320-thermal-v3-2-700296694c4a@gmail.com/ Reviewed-by: Patrice Chotard Signed-off-by: Raphael Gallais-Pou --- arch/arm/boot/dts/st/stih407-family.dtsi | 6 +++-- arch/arm/boot/dts/st/stih418.dtsi | 41 +++++++++++++++++++++++++++++--- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 29302e74aa1d..35a55aef7f4b 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -33,7 +33,7 @@ delta_reserved: rproc@44000000 { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -52,8 +52,9 @@ cpu@0 { clock-latency = <100000>; cpu0-supply = <&pwm_regulator>; st,syscfg = <&syscfg_core 0x8e0>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -66,6 +67,7 @@ cpu@1 { 1200000 0 800000 0 500000 0>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index b35b9b7a7ccc..6622ffa8ecfa 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -6,23 +6,26 @@ #include "stih418-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; }; @@ -44,6 +47,38 @@ usb2_picophy2: phy3 { reset-names = "global", "port"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + + thermal-sensors = <&thermal>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { rng11: rng@8a8a000 { status = "disabled"; @@ -107,7 +142,7 @@ mmc0: sdhci@9060000 { assigned-clock-rates = <200000000>; }; - thermal@91a0000 { + thermal: thermal@91a0000 { compatible = "st,stih407-thermal"; reg = <0x91a0000 0x28>; clock-names = "thermal";