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Wed, 26 Jun 2024 14:31:07 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:31:02 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 5/6] iommu/arm-smmu: add ACTLR data and support for SC7280 Date: Wed, 26 Jun 2024 20:00:19 +0530 Message-ID: <20240626143020.3682243-6-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: stVHse33-NhFiiEb_0S4KNK-WTAP6sqN X-Proofpoint-ORIG-GUID: stVHse33-NhFiiEb_0S4KNK-WTAP6sqN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240626_073117_969120_17C0F8D4 X-CRM114-Status: GOOD ( 13.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add ACTLR data table for SC7280 along with support for same including SC7280 specific implementation operations. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 58 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b4521471ffe9..bd101a161d04 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -29,6 +29,55 @@ #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) #define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +static const struct actlr_config sc7280_apps_actlr_cfg[] = { + { 0x0800, 0x04e0, PREFETCH_DEFAULT | CMTLB }, + { 0x2040, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x2000, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x2062, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x2080, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x20c0, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x2100, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x2140, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x0900, 0x0402, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x0901, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x0d01, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1181, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1182, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1183, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1184, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1185, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1186, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1187, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1188, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1189, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118b, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118c, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118d, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118e, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118f, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x2180, 0x0020, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2181, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2183, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2184, 0x0020, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2187, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, +}; + +static const struct actlr_config sc7280_gfx_actlr_cfg[] = { + { 0x0000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB }, +}; + +static const struct actlr_variant sc7280_actlr[] = { + { + .io_start = 0x15000000, + .actlrcfg = sc7280_apps_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sc7280_apps_actlr_cfg) + }, { + .io_start = 0x03da0000, + .actlrcfg = sc7280_gfx_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sc7280_gfx_actlr_cfg) + }, +}; + static const struct actlr_config sm8550_apps_actlr_cfg[] = { { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, @@ -685,6 +734,13 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; +static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = { + .impl = &qcom_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrvar = sc7280_actlr, + .num_smmu = ARRAY_SIZE(sc7280_actlr), +}; static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, @@ -711,7 +767,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, - { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, + { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_500_impl0_data }, { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },