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ARM: mmu: Do not use magic number for TTBCR settings

Message ID 20240701-arm-ttbcr-cleanup-v1-1-2f97268f381c@linaro.org (mailing list archive)
State New, archived
Headers show
Series ARM: mmu: Do not use magic number for TTBCR settings | expand

Commit Message

Linus Walleij July 1, 2024, 7:42 a.m. UTC 
The code in early_paging_init is directly masking off bits
8, 9, 10 and 11 to temporarily disable caching of the translation
tables. There is some exlanations in the comment, but use some
defines instead of magic numbers so ut becomes more evident
what is going on.

Change the type of the register to u32 since these are indeed
unsigned 32bit registers, and use a temporary variable instead
of baking too much into the inline assembly call to increase
readability.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 arch/arm/include/asm/pgtable-3level-hwdef.h | 5 +++++
 arch/arm/mm/mmu.c                           | 6 ++++--
 2 files changed, 9 insertions(+), 2 deletions(-)


---
base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
change-id: 20240701-arm-ttbcr-cleanup-323ff4a666a1

Best regards,
diff mbox series

Patch

diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index dfab3e982cbf..944fc9955528 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -106,6 +106,11 @@ 
 
 /*
  * TTBCR register bits.
+ *
+ * The ORGN0 and IRGN0 bits enables different forms of caching when
+ * walking the translation table. Clearing these bits (which is claimed
+ * to be the reset default) means "normal memory, [outer|inner]
+ * non-cacheable"
  */
 #define TTBCR_EAE		(1 << 31)
 #define TTBCR_IMP		(1 << 30)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3f774856ca67..f85c177cdf8d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1638,7 +1638,7 @@  static void __init early_paging_init(const struct machine_desc *mdesc)
 {
 	pgtables_remap *lpae_pgtables_remap;
 	unsigned long pa_pgd;
-	unsigned int cr, ttbcr;
+	u32 cr, ttbcr, tmp;
 	long long offset;
 
 	if (!mdesc->pv_fixup)
@@ -1688,7 +1688,9 @@  static void __init early_paging_init(const struct machine_desc *mdesc)
 	cr = get_cr();
 	set_cr(cr & ~(CR_I | CR_C));
 	ttbcr = cpu_get_ttbcr();
-	cpu_set_ttbcr(ttbcr & ~(3 << 8 | 3 << 10));
+	/* Disable all kind of caching of the translation table */
+	tmp = ttbcr & ~(TTBCR_ORGN0_MASK | TTBCR_IRGN0_MASK);
+	cpu_set_ttbcr(tmp);
 	flush_cache_all();
 
 	/*