| Message ID | 20240701-imx8qm-dts-usb-v4-2-03cdbc8c44b6@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8qm: add subsystem lvds and mipi | expand |
On Mon, Jul 01, 2024 at 11:03:28AM -0400, Frank Li wrote: > Add irqsteer, pwm and i2c in lvds subsystem. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 77 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 10 +++ > 2 files changed, 87 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi > new file mode 100644 > index 0000000000000..1da3934847057 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright 2024 NXP > + */ > + > +&qm_lvds0_lis_lpcg { > + clocks = <&lvds_ipg_clk>; > + clock-indices = <IMX_LPCG_CLK_4>; > +}; > + > +&qm_lvds0_pwm_lpcg { > + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, > + <&lvds_ipg_clk>; > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > +}; > + > +&qm_lvds0_i2c0_lpcg { > + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, > + <&lvds_ipg_clk>; > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > +}; > + > +&qm_pwm_lvds0 { > + clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>, > + <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>; > +}; > + > +&qm_i2c0_lvds0 { > + clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>, > + <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>; > +}; > + > +&lvds0_subsys { > + interrupt-parent = <&irqsteer_lvds0>; > + > + irqsteer_lvds0: interrupt-controller@56240000 { > + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; Is compatible "fsl,imx8qm-irqsteer" documented in bindings? Shawn > + reg = <0x56240000 0x1000>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + interrupt-parent = <&gic>; > + #interrupt-cells = <1>; > + clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>; > + clock-names = "ipg"; > + power-domains = <&pd IMX_SC_R_LVDS_0>; > + > + fsl,channel = <0>; > + fsl,num-irqs = <32>; > + }; > + > + lvds0_i2c1_lpcg: clock-controller@56243014 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x56243014 0x4>; > + #clock-cells = <1>; > + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, > + <&lvds_ipg_clk>; > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > + clock-output-names = "lvds0_i2c1_lpcg_clk", > + "lvds0_i2c1_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; > + }; > + > + i2c1_lvds0: i2c@56247000 { > + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg = <0x56247000 0x1000>; > + interrupts = <9>; > + clocks = <&lvds0_i2c1_lpcg IMX_LPCG_CLK_0>, > + <&lvds0_i2c1_lpcg IMX_LPCG_CLK_4>; > + clock-names = "per", "ipg"; > + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <24000000>; > + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; > + status = "disabled"; > + }; > +}; > + > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > index 61986e0639e53..1e8511e8d8577 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > @@ -560,11 +560,20 @@ clk_spdif1_rx: clock-spdif1-rx { > clock-output-names = "spdif1_rx"; > }; > > + lvds_ipg_clk: clock-controller-lvds-ipg { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "lvds0_ipg_clk"; > + }; > + > /* sorted in register address */ > #include "imx8-ss-cm41.dtsi" > #include "imx8-ss-audio.dtsi" > #include "imx8-ss-vpu.dtsi" > #include "imx8-ss-gpu0.dtsi" > + #include "imx8-ss-lvds0.dtsi" > + #include "imx8-ss-lvds1.dtsi" > #include "imx8-ss-img.dtsi" > #include "imx8-ss-dma.dtsi" > #include "imx8-ss-conn.dtsi" > @@ -576,3 +585,4 @@ clk_spdif1_rx: clock-spdif1-rx { > #include "imx8qm-ss-conn.dtsi" > #include "imx8qm-ss-lsio.dtsi" > #include "imx8qm-ss-audio.dtsi" > +#include "imx8qm-ss-lvds.dtsi" > > -- > 2.34.1 >
On Tue, Jul 02, 2024 at 12:10:58PM +0800, Shawn Guo wrote: > On Mon, Jul 01, 2024 at 11:03:28AM -0400, Frank Li wrote: > > Add irqsteer, pwm and i2c in lvds subsystem. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 77 +++++++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 10 +++ > > 2 files changed, 87 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi > > new file mode 100644 > > index 0000000000000..1da3934847057 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi > > @@ -0,0 +1,77 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +/* > > + * Copyright 2024 NXP > > + */ > > + > > +&qm_lvds0_lis_lpcg { > > + clocks = <&lvds_ipg_clk>; > > + clock-indices = <IMX_LPCG_CLK_4>; > > +}; > > + > > +&qm_lvds0_pwm_lpcg { > > + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, > > + <&lvds_ipg_clk>; > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > > +}; > > + > > +&qm_lvds0_i2c0_lpcg { > > + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, > > + <&lvds_ipg_clk>; > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > > +}; > > + > > +&qm_pwm_lvds0 { > > + clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>, > > + <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>; > > +}; > > + > > +&qm_i2c0_lvds0 { > > + clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>, > > + <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>; > > +}; > > + > > +&lvds0_subsys { > > + interrupt-parent = <&irqsteer_lvds0>; > > + > > + irqsteer_lvds0: interrupt-controller@56240000 { > > + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; > > Is compatible "fsl,imx8qm-irqsteer" documented in bindings? In rob' tree https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/commit/?h=dt/next&id=285c645d842c5a15d3be2d653faaa5f68d81be1f Frank > > Shawn > > > + reg = <0x56240000 0x1000>; > > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + interrupt-parent = <&gic>; > > + #interrupt-cells = <1>; > > + clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>; > > + clock-names = "ipg"; > > + power-domains = <&pd IMX_SC_R_LVDS_0>; > > + > > + fsl,channel = <0>; > > + fsl,num-irqs = <32>; > > + }; > > + > > + lvds0_i2c1_lpcg: clock-controller@56243014 { > > + compatible = "fsl,imx8qxp-lpcg"; > > + reg = <0x56243014 0x4>; > > + #clock-cells = <1>; > > + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, > > + <&lvds_ipg_clk>; > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > > + clock-output-names = "lvds0_i2c1_lpcg_clk", > > + "lvds0_i2c1_lpcg_ipg_clk"; > > + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; > > + }; > > + > > + i2c1_lvds0: i2c@56247000 { > > + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; > > + reg = <0x56247000 0x1000>; > > + interrupts = <9>; > > + clocks = <&lvds0_i2c1_lpcg IMX_LPCG_CLK_0>, > > + <&lvds0_i2c1_lpcg IMX_LPCG_CLK_4>; > > + clock-names = "per", "ipg"; > > + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; > > + assigned-clock-rates = <24000000>; > > + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; > > + status = "disabled"; > > + }; > > +}; > > + > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > > index 61986e0639e53..1e8511e8d8577 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > > @@ -560,11 +560,20 @@ clk_spdif1_rx: clock-spdif1-rx { > > clock-output-names = "spdif1_rx"; > > }; > > > > + lvds_ipg_clk: clock-controller-lvds-ipg { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + clock-output-names = "lvds0_ipg_clk"; > > + }; > > + > > /* sorted in register address */ > > #include "imx8-ss-cm41.dtsi" > > #include "imx8-ss-audio.dtsi" > > #include "imx8-ss-vpu.dtsi" > > #include "imx8-ss-gpu0.dtsi" > > + #include "imx8-ss-lvds0.dtsi" > > + #include "imx8-ss-lvds1.dtsi" > > #include "imx8-ss-img.dtsi" > > #include "imx8-ss-dma.dtsi" > > #include "imx8-ss-conn.dtsi" > > @@ -576,3 +585,4 @@ clk_spdif1_rx: clock-spdif1-rx { > > #include "imx8qm-ss-conn.dtsi" > > #include "imx8qm-ss-lsio.dtsi" > > #include "imx8qm-ss-audio.dtsi" > > +#include "imx8qm-ss-lvds.dtsi" > > > > -- > > 2.34.1 > > >
On Tue, Jul 02, 2024 at 12:22:37AM -0400, Frank Li wrote: > On Tue, Jul 02, 2024 at 12:10:58PM +0800, Shawn Guo wrote: > > On Mon, Jul 01, 2024 at 11:03:28AM -0400, Frank Li wrote: > > > Add irqsteer, pwm and i2c in lvds subsystem. > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > > --- > > > arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 77 +++++++++++++++++++++++ > > > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 10 +++ > > > 2 files changed, 87 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi > > > new file mode 100644 > > > index 0000000000000..1da3934847057 > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi > > > @@ -0,0 +1,77 @@ > > > +// SPDX-License-Identifier: GPL-2.0+ > > > + > > > +/* > > > + * Copyright 2024 NXP > > > + */ > > > + > > > +&qm_lvds0_lis_lpcg { > > > + clocks = <&lvds_ipg_clk>; > > > + clock-indices = <IMX_LPCG_CLK_4>; > > > +}; > > > + > > > +&qm_lvds0_pwm_lpcg { > > > + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, > > > + <&lvds_ipg_clk>; > > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > > > +}; > > > + > > > +&qm_lvds0_i2c0_lpcg { > > > + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, > > > + <&lvds_ipg_clk>; > > > + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; > > > +}; > > > + > > > +&qm_pwm_lvds0 { > > > + clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>, > > > + <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>; > > > +}; > > > + > > > +&qm_i2c0_lvds0 { > > > + clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>, > > > + <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>; > > > +}; > > > + > > > +&lvds0_subsys { > > > + interrupt-parent = <&irqsteer_lvds0>; > > > + > > > + irqsteer_lvds0: interrupt-controller@56240000 { > > > + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; > > > > Is compatible "fsl,imx8qm-irqsteer" documented in bindings? > > In rob' tree > > https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git/commit/?h=dt/next&id=285c645d842c5a15d3be2d653faaa5f68d81be1f I do not see "fsl,imx8qm-irqsteer" in the patch. Shawn
Hi Shawn,
On Tue, Jul 2, 2024 at 3:18 AM Shawn Guo <shawnguo2@yeah.net> wrote:
> I do not see "fsl,imx8qm-irqsteer" in the patch.
I sent a patch for it yesterday:
https://lore.kernel.org/linux-devicetree/1c1e3224-1b3d-438c-bce4-56143292462c@kernel.org/
On Tue, Jul 02, 2024 at 07:56:03AM -0300, Fabio Estevam wrote: > Hi Shawn, > > On Tue, Jul 2, 2024 at 3:18 AM Shawn Guo <shawnguo2@yeah.net> wrote: > > > I do not see "fsl,imx8qm-irqsteer" in the patch. > > I sent a patch for it yesterday: > > https://lore.kernel.org/linux-devicetree/1c1e3224-1b3d-438c-bce4-56143292462c@kernel.org/ I applied the series. Please help push the bindings update to get landed. Shawn
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi new file mode 100644 index 0000000000000..1da3934847057 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2024 NXP + */ + +&qm_lvds0_lis_lpcg { + clocks = <&lvds_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; +}; + +&qm_lvds0_pwm_lpcg { + clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; +}; + +&qm_lvds0_i2c0_lpcg { + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; +}; + +&qm_pwm_lvds0 { + clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>, + <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>; +}; + +&qm_i2c0_lvds0 { + clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>, + <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>; +}; + +&lvds0_subsys { + interrupt-parent = <&irqsteer_lvds0>; + + irqsteer_lvds0: interrupt-controller@56240000 { + compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + fsl,channel = <0>; + fsl,num-irqs = <32>; + }; + + lvds0_i2c1_lpcg: clock-controller@56243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "lvds0_i2c1_lpcg_clk", + "lvds0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56247000 0x1000>; + interrupts = <9>; + clocks = <&lvds0_i2c1_lpcg IMX_LPCG_CLK_0>, + <&lvds0_i2c1_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 61986e0639e53..1e8511e8d8577 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -560,11 +560,20 @@ clk_spdif1_rx: clock-spdif1-rx { clock-output-names = "spdif1_rx"; }; + lvds_ipg_clk: clock-controller-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds0_ipg_clk"; + }; + /* sorted in register address */ #include "imx8-ss-cm41.dtsi" #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-gpu0.dtsi" + #include "imx8-ss-lvds0.dtsi" + #include "imx8-ss-lvds1.dtsi" #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" @@ -576,3 +585,4 @@ clk_spdif1_rx: clock-spdif1-rx { #include "imx8qm-ss-conn.dtsi" #include "imx8qm-ss-lsio.dtsi" #include "imx8qm-ss-audio.dtsi" +#include "imx8qm-ss-lvds.dtsi"
Add irqsteer, pwm and i2c in lvds subsystem. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 77 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 10 +++ 2 files changed, 87 insertions(+)