| Message ID | 20240702091349.356008-1-kevin.brodsky@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Documentation: arm64: Update memory.rst for TBI | expand |
On Tue, Jul 02, 2024 at 10:13:49AM +0100, Kevin Brodsky wrote: > Most of memory.rst was written very early, at a time where TBI (Top > Byte Ignore) was not enabled. Nowadays TBI0 is always enabled, and > TBI1 may be enabled, depending on the kernel configuration. This > means that VA bits 63:56 cannot generally be assumed to have any > particular value. > > Regardless of TBI, TTBRx selection is done based on bit 55; update > memory.rst accordingly. > > Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > Documentation/arch/arm64/memory.rst | 42 ++++++++++++++--------------- > 1 file changed, 20 insertions(+), 22 deletions(-) > > diff --git a/Documentation/arch/arm64/memory.rst b/Documentation/arch/arm64/memory.rst > index 55a55f30eed8..8a658984b8bb 100644 > --- a/Documentation/arch/arm64/memory.rst > +++ b/Documentation/arch/arm64/memory.rst > @@ -18,12 +18,10 @@ ARMv8.2 adds optional support for Large Virtual Address space. This is > only available when running with a 64KB page size and expands the > number of descriptors in the first level of translation. > > -User addresses have bits 63:48 set to 0 while the kernel addresses have > -the same bits set to 1. TTBRx selection is given by bit 63 of the > -virtual address. The swapper_pg_dir contains only kernel (global) > -mappings while the user pgd contains only user (non-global) mappings. > -The swapper_pg_dir address is written to TTBR1 and never written to > -TTBR0. > +TTBRx selection is given by bit 55 of the virtual address. The > +swapper_pg_dir contains only kernel (global) mappings while the user pgd > +contains only user (non-global) mappings. The swapper_pg_dir address is > +written to TTBR1 and never written to TTBR0. > > > AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit):: > @@ -65,14 +63,14 @@ Translation table lookup with 4KB pages:: > +--------+--------+--------+--------+--------+--------+--------+--------+ > |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| > +--------+--------+--------+--------+--------+--------+--------+--------+ > - | | | | | | > - | | | | | v > - | | | | | [11:0] in-page offset > - | | | | +-> [20:12] L3 index > - | | | +-----------> [29:21] L2 index > - | | +---------------------> [38:30] L1 index > - | +-------------------------------> [47:39] L0 index > - +-------------------------------------------------> [63] TTBR0/1 > + | | | | | | > + | | | | | v > + | | | | | [11:0] in-page offset > + | | | | +-> [20:12] L3 index > + | | | +-----------> [29:21] L2 index > + | | +---------------------> [38:30] L1 index > + | +-------------------------------> [47:39] L0 index > + +----------------------------------------> [55] TTBR0/1 > > > Translation table lookup with 64KB pages:: > @@ -80,14 +78,14 @@ Translation table lookup with 64KB pages:: > +--------+--------+--------+--------+--------+--------+--------+--------+ > |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| > +--------+--------+--------+--------+--------+--------+--------+--------+ > - | | | | | > - | | | | v > - | | | | [15:0] in-page offset > - | | | +----------> [28:16] L3 index > - | | +--------------------------> [41:29] L2 index > - | +-------------------------------> [47:42] L1 index (48-bit) > - | [51:42] L1 index (52-bit) > - +-------------------------------------------------> [63] TTBR0/1 > + | | | | | > + | | | | v > + | | | | [15:0] in-page offset > + | | | +----------> [28:16] L3 index > + | | +--------------------------> [41:29] L2 index > + | +-------------------------------> [47:42] L1 index (48-bit) > + | [51:42] L1 index (52-bit) > + +----------------------------------------> [55] TTBR0/1 > > > When using KVM without the Virtualization Host Extensions, the > -- > 2.43.0 >
On Tue, 02 Jul 2024 10:13:49 +0100, Kevin Brodsky wrote: > Most of memory.rst was written very early, at a time where TBI (Top > Byte Ignore) was not enabled. Nowadays TBI0 is always enabled, and > TBI1 may be enabled, depending on the kernel configuration. This > means that VA bits 63:56 cannot generally be assumed to have any > particular value. > > Regardless of TBI, TTBRx selection is done based on bit 55; update > memory.rst accordingly. > > [...] Applied to arm64 (for-next/doc), thanks! [1/1] Documentation: arm64: Update memory.rst for TBI https://git.kernel.org/arm64/c/5e30c16b58a4
diff --git a/Documentation/arch/arm64/memory.rst b/Documentation/arch/arm64/memory.rst index 55a55f30eed8..8a658984b8bb 100644 --- a/Documentation/arch/arm64/memory.rst +++ b/Documentation/arch/arm64/memory.rst @@ -18,12 +18,10 @@ ARMv8.2 adds optional support for Large Virtual Address space. This is only available when running with a 64KB page size and expands the number of descriptors in the first level of translation. -User addresses have bits 63:48 set to 0 while the kernel addresses have -the same bits set to 1. TTBRx selection is given by bit 63 of the -virtual address. The swapper_pg_dir contains only kernel (global) -mappings while the user pgd contains only user (non-global) mappings. -The swapper_pg_dir address is written to TTBR1 and never written to -TTBR0. +TTBRx selection is given by bit 55 of the virtual address. The +swapper_pg_dir contains only kernel (global) mappings while the user pgd +contains only user (non-global) mappings. The swapper_pg_dir address is +written to TTBR1 and never written to TTBR0. AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit):: @@ -65,14 +63,14 @@ Translation table lookup with 4KB pages:: +--------+--------+--------+--------+--------+--------+--------+--------+ |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| +--------+--------+--------+--------+--------+--------+--------+--------+ - | | | | | | - | | | | | v - | | | | | [11:0] in-page offset - | | | | +-> [20:12] L3 index - | | | +-----------> [29:21] L2 index - | | +---------------------> [38:30] L1 index - | +-------------------------------> [47:39] L0 index - +-------------------------------------------------> [63] TTBR0/1 + | | | | | | + | | | | | v + | | | | | [11:0] in-page offset + | | | | +-> [20:12] L3 index + | | | +-----------> [29:21] L2 index + | | +---------------------> [38:30] L1 index + | +-------------------------------> [47:39] L0 index + +----------------------------------------> [55] TTBR0/1 Translation table lookup with 64KB pages:: @@ -80,14 +78,14 @@ Translation table lookup with 64KB pages:: +--------+--------+--------+--------+--------+--------+--------+--------+ |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| +--------+--------+--------+--------+--------+--------+--------+--------+ - | | | | | - | | | | v - | | | | [15:0] in-page offset - | | | +----------> [28:16] L3 index - | | +--------------------------> [41:29] L2 index - | +-------------------------------> [47:42] L1 index (48-bit) - | [51:42] L1 index (52-bit) - +-------------------------------------------------> [63] TTBR0/1 + | | | | | + | | | | v + | | | | [15:0] in-page offset + | | | +----------> [28:16] L3 index + | | +--------------------------> [41:29] L2 index + | +-------------------------------> [47:42] L1 index (48-bit) + | [51:42] L1 index (52-bit) + +----------------------------------------> [55] TTBR0/1 When using KVM without the Virtualization Host Extensions, the
Most of memory.rst was written very early, at a time where TBI (Top Byte Ignore) was not enabled. Nowadays TBI0 is always enabled, and TBI1 may be enabled, depending on the kernel configuration. This means that VA bits 63:56 cannot generally be assumed to have any particular value. Regardless of TBI, TTBRx selection is done based on bit 55; update memory.rst accordingly. Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com> --- Documentation/arch/arm64/memory.rst | 42 ++++++++++++++--------------- 1 file changed, 20 insertions(+), 22 deletions(-)