| Message ID | 20240703112543.148304-1-eichest@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] serial: imx: only set receiver level if it is zero | expand |
On 03. 07. 24, 13:25, Stefan Eichenberger wrote: > From: Stefan Eichenberger <stefan.eichenberger@toradex.com> > > With commit a81dbd0463ec ("serial: imx: set receiver level before > starting uart") we set the receiver level to its default value. This > caused a regression when using SDMA, where the receiver level is 9 > instead of 8 (default). This change will first check if the receiver > level is zero and only then set it to the default. This still avoids the > interrupt storm when the receiver level is zero. > > Fixes: a81dbd0463ec ("serial: imx: set receiver level before starting uart") > Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> > --- > drivers/tty/serial/imx.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c > index f4f40c9373c2f..e22be8f45c93e 100644 > --- a/drivers/tty/serial/imx.c > +++ b/drivers/tty/serial/imx.c > @@ -120,6 +120,7 @@ > #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ > #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ > #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ > +#define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */ > #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ > #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ All these should be converted to BIT() and GENMASK(). Then, UFCR_RXTL_MASK should be obviously GENMASK(5, 0). UFCR_RXTL_SHF is unused (and unneeded) BTW. > #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) thanks,
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index f4f40c9373c2f..e22be8f45c93e 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -120,6 +120,7 @@ #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */ #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) @@ -1933,7 +1934,7 @@ static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termio struct serial_rs485 *rs485conf) { struct imx_port *sport = (struct imx_port *)port; - u32 ucr2; + u32 ucr2, ufcr; if (rs485conf->flags & SER_RS485_ENABLED) { /* Enable receiver if low-active RTS signal is requested */ @@ -1953,7 +1954,10 @@ static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termio /* Make sure Rx is enabled in case Tx is active with Rx disabled */ if (!(rs485conf->flags & SER_RS485_ENABLED) || rs485conf->flags & SER_RS485_RX_DURING_TX) { - imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); + /* If the receiver trigger is 0, set it to a default value */ + ufcr = imx_uart_readl(sport, UFCR); + if ((ufcr & UFCR_RXTL_MASK) == 0) + imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); imx_uart_start_rx(port); }