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[v3,04/10] irqchip/armada-370-xp: Use BIT() and GENMASK() macros

Message ID 20240708151801.11592-5-kabel@kernel.org (mailing list archive)
State New, archived
Headers show
Series armada-370-xp irqchip updates round 2 | expand

Commit Message

Marek Behún July 8, 2024, 3:17 p.m. UTC 
Use the BIT() and GENMASK() macros where appropriate.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
 drivers/irqchip/irq-armada-370-xp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Ilpo Järvinen July 8, 2024, 4:27 p.m. UTC | #1 
On Mon, 8 Jul 2024, Marek Behún wrote:

> Use the BIT() and GENMASK() macros where appropriate.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>

Are #includes missing for GENMASK() and BIT()? (Or is this based on some 
tree which already has them?)
Marek Behún July 9, 2024, 6:54 a.m. UTC | #2 
On Mon, 8 Jul 2024 19:27:52 +0300 (EEST)
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:

> On Mon, 8 Jul 2024, Marek Behún wrote:
> 
> > Use the BIT() and GENMASK() macros where appropriate.
> > 
> > Signed-off-by: Marek Behún <kabel@kernel.org>
> > Reviewed-by: Andrew Lunn <andrew@lunn.ch>  
> 
> Are #includes missing for GENMASK() and BIT()? (Or is this based on some 
> tree which already has them?)

#include <linux/bits.h> was added in another patch that was already
accepted to tip.git irq/core branch (and merged into tip.git master
branch):
  https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=986b6ad0c4c653940fab7e5decf0d847670bf407

Marek
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 427ba5fd6adc..18aca9b5d3b3 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -121,7 +121,7 @@ 
 #define ARMADA_370_XP_INT_SET_ENABLE		(0x30)
 #define ARMADA_370_XP_INT_CLEAR_ENABLE		(0x34)
 #define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
-#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF
+#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	GENMASK(3, 0)
 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)	((BIT(0) | BIT(8)) << cpuid)
 
 /* Registers relative to per_cpu_int_base */
@@ -132,18 +132,18 @@ 
 #define ARMADA_370_XP_INT_SET_MASK		(0x48)
 #define ARMADA_370_XP_INT_CLEAR_MASK		(0x4C)
 #define ARMADA_370_XP_INT_FABRIC_MASK		(0x54)
-#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)
+#define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	BIT(cpu)
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)
 
 /* IPI and MSI interrupt definitions for IPI platforms */
 #define IPI_DOORBELL_START			(0)
 #define IPI_DOORBELL_END			(8)
-#define IPI_DOORBELL_MASK			0xFF
+#define IPI_DOORBELL_MASK			GENMASK(7, 0)
 #define PCI_MSI_DOORBELL_START			(16)
 #define PCI_MSI_DOORBELL_NR			(16)
 #define PCI_MSI_DOORBELL_END			(32)
-#define PCI_MSI_DOORBELL_MASK			0xFFFF0000
+#define PCI_MSI_DOORBELL_MASK			GENMASK(31, 16)
 
 /* MSI interrupt definitions for non-IPI platforms */
 #define PCI_MSI_FULL_DOORBELL_START		0
@@ -415,7 +415,7 @@  static void armada_370_xp_ipi_send_mask(struct irq_data *d,
 
 	/* Convert our logical CPU mask into a physical one. */
 	for_each_cpu(cpu, mask)
-		map |= 1 << cpu_logical_map(cpu);
+		map |= BIT(cpu_logical_map(cpu));
 
 	/*
 	 * Ensure that stores to Normal memory are visible to the