From patchwork Wed Jul 10 22:16:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13729779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CFC5C3DA42 for ; Wed, 10 Jul 2024 22:20:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Reply-To:MIME-Version: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9STkE/nXLSa9GNLPreO/fiNAxJRnRMjsLIRLoy/pbq4=; b=wtITOMlmLxnrU5r+cdibnUKC9h STX0PHy7oDIILqCymPRTy/Guwq/Fk1TtBfQ7VN7uiYQxpBR2mMomCouKuntoivscop7RD0bxcYz0G uLo35ZHE6wDFbb+Y/8OWi7Ru7EWPEANP08mHgFRZTmEah/i/UmPep+LuGcDIUDYbDS5KWHkPoemrU L8P9DjciVMbGRTtqu67uF8JUTM5ddDqzDziNPjz2EjDc0ofFrEEIWJ0mlWMdzaIBSOpwJuSJLrY4S 3LvOPLurP1Bmz4k46Rp4+gof5/9hgbGy76JPpSN2K1SPybrIBBGebqJAfhh6Ryn4gvGHlrvxFUdfo X8urezQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRfft-0000000Bvb2-35m7; Wed, 10 Jul 2024 22:20:33 +0000 Received: from mail-qv1-xf36.google.com ([2607:f8b0:4864:20::f36]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRfcL-0000000Bu1n-1cyw for linux-arm-kernel@lists.infradead.org; Wed, 10 Jul 2024 22:16:55 +0000 Received: by mail-qv1-xf36.google.com with SMTP id 6a1803df08f44-6b5ec93f113so1535726d6.3 for ; Wed, 10 Jul 2024 15:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1720649812; x=1721254612; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=9STkE/nXLSa9GNLPreO/fiNAxJRnRMjsLIRLoy/pbq4=; b=TAQneNWcHGa2fPoSVULVrMjWFiuGSFEbNO2ml/bzPUBzXR7pGqDyi4xD6fzLR+TRkd huzgmJy8bL1K/IszgubcGH+2ADKAA27FvGx6xIku22R5GWT56rmc8+JgxQlH/E6B91ca rxNMeZrwfjdfc6ovRTkQKYk5fch4DvP7HgYis= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720649812; x=1721254612; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9STkE/nXLSa9GNLPreO/fiNAxJRnRMjsLIRLoy/pbq4=; b=dM0asvo8qRFOeMEfS7IY6HbQEphSZRx7IMbQLRmg3ZPCU+C3vUvrZZRkjkXdPswAmM EW0r0ti6DcPHTYPh4Q/sqva5Y0I7ih4mLmsbRfwhSLyFeBsezK0VMl6TvZ7JPU9PMj3f LG/SQRxZsWTOJz4tCmZh4KUSZRpy58fcf2SA2rLZeGvUnEo1CQ6AmEQ51cFL3NSrpl3d 32NfNL8JTDhBluBuNrzCl4G1Tcjmjzywexm+8Y4Ub5e5NCtCStIQR158XileOL3iuU3l vTrpUielCUBUlIwU2MO/QdYK4TxpPydpVGz1sW30LPi16Vup3qgcOFRTQwdZgRr0QGrh AeAQ== X-Forwarded-Encrypted: i=1; AJvYcCXCiyyPDdHwsOZp5iQDrfYs964dUqQ6cTZpSkWQt6pF7uUx71r/cqJyGOf8nwjkgP5jGXLIFuQVw6Ywnj9b5mgdFU6iiaOccHAjP8AP3DpGioMSaE0= X-Gm-Message-State: AOJu0YzDs2VKW9f5YqV1nIvzbFY+IVacyfJIiSUaQ8a1WaMAeh+nL9eE fKtJKYz2zJc1zWnUxEozlSBj7v4FuydbsMBes3+0xAf4w/WWTYKmeWbpauYndw== X-Google-Smtp-Source: AGHT+IEMb5nEAz7tzkCTjFEGV0o1p4WI3LHzasNhvhgrx5PZeTFAuauj/wfrj7OSOBKyVHxmHXl+nQ== X-Received: by 2002:ad4:5f45:0:b0:6b2:ba66:81e9 with SMTP id 6a1803df08f44-6b61c1fa6ccmr81451616d6.62.1720649812351; Wed, 10 Jul 2024 15:16:52 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b61ba04c16sm20182326d6.60.2024.07.10.15.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jul 2024 15:16:51 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 11/12] PCI: brcmstb: Change field name from 'type' to 'model' Date: Wed, 10 Jul 2024 18:16:25 -0400 Message-Id: <20240710221630.29561-12-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240710221630.29561-1-james.quinlan@broadcom.com> References: <20240710221630.29561-1-james.quinlan@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240710_151653_542849_5B4C5417 X-CRM114-Status: GOOD ( 20.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 'type' field used in the driver to discern SoC differences is confusing so change it to the more apt 'model'. We considered using 'family' but this conflicts with Broadcom's conception of a family; for example, 7216a0 and 7216b0 chips are both considered separate families as each has multiple derivative product chips based on the original design. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index c334cc427fb7..b6b21e0a56a8 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -211,7 +211,7 @@ enum { PCIE_INTR2_CPU_BASE, }; -enum pcie_type { +enum pcie_model { GENERIC, BCM7425, BCM7435, @@ -229,7 +229,7 @@ struct rc_bar { struct pcie_cfg_data { const int *offsets; - const enum pcie_type type; + const enum pcie_model model; const bool has_phy; unsigned int num_inbound; int (*perst_set)(struct brcm_pcie *pcie, u32 val); @@ -270,7 +270,7 @@ struct brcm_pcie { u64 msi_target_addr; struct brcm_msi *msi; const int *reg_offsets; - enum pcie_type type; + enum pcie_model model; struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge; @@ -288,7 +288,7 @@ struct brcm_pcie { static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->type == BCM7435 || pcie->type == BCM7425; + return pcie->model == BCM7435 || pcie->model == BCM7425; } /* @@ -851,7 +851,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * security considerations, and is not implemented in our modern * SoCs. */ - if (pcie->type != BCM7712) + if (pcie->model != BCM7712) set_bar(b++, &n, 0, 0, 0); resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -868,7 +868,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * That being said, each BARs size must still be a power of * two. */ - if (pcie->type == BCM7712) + if (pcie->model == BCM7712) set_bar(b++, &n, size, cpu_beg, pcie_beg); if (n > pcie->num_inbound) @@ -885,7 +885,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * that enables multiple memory controllers. As such, it can return * now w/o doing special configuration. */ - if (pcie->type == BCM7712) + if (pcie->model == BCM7712) return n; ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, @@ -1007,7 +1007,7 @@ static void set_inbound_win_registers(struct brcm_pcie *pcie, const struct rc_ba * 7712: * All of their BARs need to be set. */ - if (pcie->type == BCM7712) { + if (pcie->model == BCM7712) { /* BUS remap register settings */ reg_offset = brcm_ubus_reg_offset(i); tmp = lower_32_bits(cpu_addr) & ~0xfff; @@ -1035,7 +1035,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return ret; /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type == BCM2711) { + if (pcie->model == BCM2711) { ret = pcie->perst_set(pcie, 1); if (ret) { pcie->bridge_sw_init_set(pcie, 0); @@ -1066,9 +1066,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst = 0x1; /* 256 bytes */ - else if (pcie->type == BCM2711) + else if (pcie->model == BCM2711) burst = 0x0; /* 128 bytes */ - else if (pcie->type == BCM7278) + else if (pcie->model == BCM7278) burst = 0x3; /* 512 bytes */ else burst = 0x2; /* 512 bytes */ @@ -1665,7 +1665,7 @@ static const int pcie_offsets_bmips_7425[] = { static const struct pcie_cfg_data generic_cfg = { .offsets = pcie_offsets, - .type = GENERIC, + .model = GENERIC, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1673,7 +1673,7 @@ static const struct pcie_cfg_data generic_cfg = { static const struct pcie_cfg_data bcm7425_cfg = { .offsets = pcie_offsets_bmips_7425, - .type = BCM7425, + .model = BCM7425, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1681,7 +1681,7 @@ static const struct pcie_cfg_data bcm7425_cfg = { static const struct pcie_cfg_data bcm7435_cfg = { .offsets = pcie_offsets, - .type = BCM7435, + .model = BCM7435, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1689,7 +1689,7 @@ static const struct pcie_cfg_data bcm7435_cfg = { static const struct pcie_cfg_data bcm4908_cfg = { .offsets = pcie_offsets, - .type = BCM4908, + .model = BCM4908, .perst_set = brcm_pcie_perst_set_4908, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1705,7 +1705,7 @@ static const int pcie_offset_bcm7278[] = { static const struct pcie_cfg_data bcm7278_cfg = { .offsets = pcie_offset_bcm7278, - .type = BCM7278, + .model = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, .num_inbound = 3, @@ -1713,7 +1713,7 @@ static const struct pcie_cfg_data bcm7278_cfg = { static const struct pcie_cfg_data bcm2711_cfg = { .offsets = pcie_offsets, - .type = BCM2711, + .model = BCM2711, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1721,7 +1721,7 @@ static const struct pcie_cfg_data bcm2711_cfg = { static const struct pcie_cfg_data bcm7216_cfg = { .offsets = pcie_offset_bcm7278, - .type = BCM7278, + .model = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, .has_phy = true, @@ -1778,7 +1778,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->dev = &pdev->dev; pcie->np = np; pcie->reg_offsets = data->offsets; - pcie->type = data->type; + pcie->model = data->model; pcie->perst_set = data->perst_set; pcie->bridge_sw_init_set = data->bridge_sw_init_set; pcie->has_phy = data->has_phy; @@ -1847,7 +1847,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { + if (pcie->model == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret = -ENODEV; goto fail; @@ -1862,7 +1862,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) } } - bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; + bridge->ops = pcie->model == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; bridge->sysdata = pcie; platform_set_drvdata(pdev, pcie);