From patchwork Wed Jul 10 22:16:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13729772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D507DC3DA42 for ; Wed, 10 Jul 2024 22:18:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Reply-To:MIME-Version: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VMQavjXRDGGsFib2hEcP7EEO/eQ2OugbTQ/0Bjwg9j4=; b=Yswvh81SzqbTucEdaGFYlOLyGU HyWDfi5kRCUwyNmyt37V1J3GmyUen9vWfab1Eqjddu2ukFyCZzOjJVUYTnev1Cm5uvjVs8nakymEC aNHAhSP5QOSb+yDBnENS5GnLBp2muPjBjDgVm6mIeqz7s482z2xduSmPNpRh0UTIV/zCr0Maev6hD iau5C89mBkB7a6iEn+VdUj8m4oFFoYDIk0pR383A+CmHfRkh0yu4FuzqyaF7SYtlFHkbuQZzuKkOq laUNN8ImpZ7KcBGCklyZirgXMJ1jrSlGFV510V7ztFDP1iop7wC51vRzryDODGRFqhD5A+W9OORzx qOwjnq1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRfdf-0000000Bub7-2Leq; Wed, 10 Jul 2024 22:18:15 +0000 Received: from mail-qv1-xf29.google.com ([2607:f8b0:4864:20::f29]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRfcA-0000000Btse-0orR for linux-arm-kernel@lists.infradead.org; Wed, 10 Jul 2024 22:16:43 +0000 Received: by mail-qv1-xf29.google.com with SMTP id 6a1803df08f44-6b2c6291038so2606796d6.0 for ; Wed, 10 Jul 2024 15:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1720649801; x=1721254601; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=VMQavjXRDGGsFib2hEcP7EEO/eQ2OugbTQ/0Bjwg9j4=; b=Vj2d/0WHEWAn2yGvp/B/3+De5eqdJMx637xPGUUmbblRKXksvHMMdf7PTSXq/KNDe+ XtGFlzKc0osU6tFbZXRf1A1bkZDEJPsXyC34NV035epFgN5mjCn3zTU7l/I+6iMN/I8S udIkm/+EBw0KRVTzXWFQ355G4zhaC8g563Mwk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720649801; x=1721254601; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VMQavjXRDGGsFib2hEcP7EEO/eQ2OugbTQ/0Bjwg9j4=; b=UZ6liCSqCf4SJyJxqRIr3SFU4zoTJSMnsnwwuL61epgJ5TTbXb+612WeKGfUkoeS7G qWXaOAIMKXJvma+byaO3vy93lr0ja6INgHHdFNJoRPrZ0PzEvNPi9gM5wffuXl6CLxu8 1AAspsP4ddhjL87bG2VzUyTa6vG/MMnvIJpP///RBUJDNjyyjJiAKKggMMAwssnn/7qW UXeDDfSWQGukECfwWGYXW1a6wWNywOGpjJpXclBkqp4jEku8mt0FPmZW19LMpxknzkNc i4SrpD+7n7V8w1QPOQXrkeSCjKY1qJD4kH4N+1dU1zB8iBANmyrho2z9dOTUJfX5sKLP QJ7g== X-Forwarded-Encrypted: i=1; AJvYcCWqStq7Vyo/Z9sh4IuoJxlhOrpWTwupe2vn8rwt0EsXW6hdcwGr8WG1zTxRP17/guz/J/vB+gW4z2TvvKl+E0EFfnEMYM/VJjsWX6yzV8hZLyLZ2tU= X-Gm-Message-State: AOJu0Yz9Y1jEcAakX1nK4ae//hOzGBd+ckFROIlDkn243m9tgHw9v2yU RbVrvH08B+kEzooh2IUT+VXfuD8+xHfGMtjdKrABpwfQ7GTTDxJh7n/jZFMVhg== X-Google-Smtp-Source: AGHT+IEFszqDYHgLTXOgHqniypXaVbCrQbk7+dn4z18FToqE6q68oLFQCznDBmnR9H0GvGwhBcSjWA== X-Received: by 2002:ad4:576d:0:b0:6b5:82e1:f89e with SMTP id 6a1803df08f44-6b74af4debbmr21921196d6.9.1720649800729; Wed, 10 Jul 2024 15:16:40 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b61ba04c16sm20182326d6.60.2024.07.10.15.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jul 2024 15:16:39 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 04/12] PCI: brcmstb: Use bridge reset if available Date: Wed, 10 Jul 2024 18:16:18 -0400 Message-Id: <20240710221630.29561-5-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240710221630.29561-1-james.quinlan@broadcom.com> References: <20240710221630.29561-1-james.quinlan@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240710_151642_340332_C1355C11 X-CRM114-Status: GOOD ( 16.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 7712 SOC has a bridge reset which can be described in the device tree. If it is present, use it. Otherwise, continue to use the legacy method to reset the bridge. Signed-off-by: Jim Quinlan Reviewed-by: Stanimir Varbanov Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index c257434edc08..92816d8d215a 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -265,6 +265,7 @@ struct brcm_pcie { enum pcie_type type; struct reset_control *rescal; struct reset_control *perst_reset; + struct reset_control *bridge; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -732,12 +733,19 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus, static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) { - u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; - u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + if (pcie->bridge) { + if (val) + reset_control_assert(pcie->bridge); + else + reset_control_deassert(pcie->bridge); + } else { + u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; + u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; - tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); - tmp = (tmp & ~mask) | ((val << shift) & mask); - writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + tmp = (tmp & ~mask) | ((val << shift) & mask); + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); + } } static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) @@ -1621,6 +1629,10 @@ static int brcm_pcie_probe(struct platform_device *pdev) if (IS_ERR(pcie->perst_reset)) return PTR_ERR(pcie->perst_reset); + pcie->bridge = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); + if (IS_ERR(pcie->bridge)) + return PTR_ERR(pcie->bridge); + ret = clk_prepare_enable(pcie->clk); if (ret) { dev_err(&pdev->dev, "could not enable clock\n");