From patchwork Tue Jul 16 14:29:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13734556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2699C3DA49 for ; Tue, 16 Jul 2024 14:30:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=T1xZGu6MS1yliSzf7O6/Qq6uaYC7vNsgG3icJd6mri0=; b=AyZIo67n/8Pt7MOM6xtCRudX2I 3w1pinR82olRoTs6IQAQWy6elZlOGwfs59oFYB3WySuSfhfUbZe2fSSwqpX+9jrvq03z8eHbdQxkK xlsbA9FvQ5bt3fb+jBvmOy43UiPDvYLRkZzNsf8nAGsOrm7zDSrsJNMBKKc+Etha48OpeA8ZSXiwi tVOdHCOqTkJLRPhxnWqNYkWGRIwWqTuB0GsLWJqcP7hBXSTUG0yYg9eX0VNBtLDUZsP+YElzyLYU2 OFkgT9Q58YaubWRy6o72wIwLNeUAwhlFu/DETG9bdpWxYYveIV4C0yUAtUAQwOyTaCE35zSL2pdvz p8/RhOZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjCL-0000000AivK-1iyd; Tue, 16 Jul 2024 14:30:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTjBH-0000000AiI2-1F77 for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 14:29:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8879A11FB; Tue, 16 Jul 2024 07:29:50 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 936B53F762; Tue, 16 Jul 2024 07:29:24 -0700 (PDT) From: Luca Fancellu To: andre.przywara@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/6] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET Date: Tue, 16 Jul 2024 15:29:03 +0100 Message-Id: <20240716142906.1502802-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716142906.1502802-1-luca.fancellu@arm.com> References: <20240716142906.1502802-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_072927_408931_7FA0DD20 X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From the specification SCTLR_EL2.TSCXT is RES1 only "When FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so given that HCR_EL2.E2H is set by bootwrapper before to a value of zero, the condition above can't happen and from the specification the bit is RES0. Fix the macro removing the bit. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- v2 changes: - Add Andre R-by --- arch/aarch64/include/asm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 124ef916ddfc..846b89f8405d 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -30,8 +30,8 @@ BIT(11) | BIT(5) | BIT(4)) #define SCTLR_EL2_RES1 \ - (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) | \ - BIT(16) | BIT(11) | BIT(5) | BIT(4)) + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) | \ + BIT(11) | BIT(5) | BIT(4)) #define SCTLR_EL1_RES1 \ (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \