From patchwork Tue Jul 16 21:31:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13734983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC53DC3DA59 for ; Tue, 16 Jul 2024 21:36:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Reply-To:MIME-Version: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ktkT5o05Sva3VF6fWbFtV+mlgIYa87bgVekt+2kgd+s=; b=JZ1qnHLjx8yFEXkLU3uBlRIa+e K2QbrU1355rumDtCWmlsuJCRgGUfWXkf7s9oY72pn5RKz8cC4fQ8JXbvArVRrTP4Idl+GbV+xb3yf WRXGUMATdBFefvl1GC1XU0vTFfIXiKssHDFZ8r0zcEJ+q66Qq3Bh9Hcr3rTfQlPeHGrdoY5azlkWA dJpmuFwJWcmPfpbMFoQwsknCzp+ueRxLiNxBN2XgjRgfEksxK0ojx9G9noxogAv9ZgWuSwdiRyov2 nD5Sianar01crrbit4idxJeEPNib4zocmYsVMLcaDqut8ZOxAz7e1lB8r3UozHdpNYIsWcQRdbL1R 6P2XM1eQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTpqX-0000000Br0m-2Nx1; Tue, 16 Jul 2024 21:36:29 +0000 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTpmV-0000000BpQP-1ya0 for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2024 21:32:22 +0000 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-70b07bdbfbcso147408b3a.0 for ; Tue, 16 Jul 2024 14:32:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1721165539; x=1721770339; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=ktkT5o05Sva3VF6fWbFtV+mlgIYa87bgVekt+2kgd+s=; b=aJMqkBIiwkMpWSJD7amFV+qJ8V0fRuNDkyoadhYop6XyA+GCS9BNlK8PWLaO2wNHhI svR8S3n/ZjQ4YPUzF07pbRNZlYC6gA8tmZoURj055pv+/w+Yr6AUiGHXZ7OVtTZABF5P +Z3k0lUtyVNsRkgSX+0nrGDAt7RIGhwwXsTnQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721165539; x=1721770339; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ktkT5o05Sva3VF6fWbFtV+mlgIYa87bgVekt+2kgd+s=; b=AWYtIcM9MS5B95U5O/EyRBD6WjtZaJv6P14+Vzx87HlDKxpyJda72W97lONfAP0aVO aCUoa+60O6d/uzCrsLnZNWzSMXmkK/J/iWO7gbPjoKhmyW3UlOM0V0w1n3dLcA+zpIvY TywYRpNMIWlwwfCb6jwpcaY+T0Y6EN1gfFyUqR+Ti6bK8YBN9EwqZuPSRK1Q37JJUeN0 CJuEcbzvLGFU1cywgDRM26XUreY7lg1AzOg6wYJP8Z/0qS7e7FrcZ957+/ZHbPaiyn6B N3JWLP9mGlZXDG7ZVz6RTg33JGSnv//JMbmkWvgvvQWC9ZuStEPYKfb+B7h2s6AN3Lcw t4sw== X-Forwarded-Encrypted: i=1; AJvYcCUl5szREmCm9cVjBMYJR9SKKUhsZ6NBwHu1nyWJeyYw4uTo+ln92EnMamWGR55Hz/V9wVXROT4RgsrW4tE8BP8BXlopiEfJvLkC6GnIt7JKm2L0T0E= X-Gm-Message-State: AOJu0YyPPtiQ1rZfMVYxpiNC6Js1uAGgdtpyPDWyQ9M6XN+vguToVFdS 0Gn1MjlhvzdFtmFCjK0BUNla1oGWSxdfOcHhSg/eGaxce0F8yCAQB/6MnEXtpg== X-Google-Smtp-Source: AGHT+IGx3fCh6S2QfTNtvLqxaswCxSc1oIJxvnMZ0D0dcPdjNSV74JcS7F3v925N9gUIHSu7fi3oxg== X-Received: by 2002:a05:6a20:7487:b0:1c0:f630:97a5 with SMTP id adf61e73a8af0-1c3f1fb382amr5190270637.10.1721165538637; Tue, 16 Jul 2024 14:32:18 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b7eb9e20fsm6812828b3a.31.2024.07.16.14.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 14:32:18 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 11/12] PCI: brcmstb: Change field name from 'type' to 'model' Date: Tue, 16 Jul 2024 17:31:26 -0400 Message-Id: <20240716213131.6036-12-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240716213131.6036-1-james.quinlan@broadcom.com> References: <20240716213131.6036-1-james.quinlan@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_143219_685947_D5F732A8 X-CRM114-Status: GOOD ( 20.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 'type' field used in the driver to discern SoC differences is confusing so change it to the more apt 'model'. We considered using 'family' but this conflicts with Broadcom's conception of a family; for example, 7216a0 and 7216b0 chips are both considered separate families as each has multiple derivative product chips based on the original design. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 2fe1f2a26697..fa5616a56383 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -211,7 +211,7 @@ enum { PCIE_INTR2_CPU_BASE, }; -enum pcie_type { +enum pcie_model { GENERIC, BCM7425, BCM7435, @@ -229,7 +229,7 @@ struct rc_bar { struct pcie_cfg_data { const int *offsets; - const enum pcie_type type; + const enum pcie_model model; const bool has_phy; unsigned int num_inbound; int (*perst_set)(struct brcm_pcie *pcie, u32 val); @@ -270,7 +270,7 @@ struct brcm_pcie { u64 msi_target_addr; struct brcm_msi *msi; const int *reg_offsets; - enum pcie_type type; + enum pcie_model model; struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge; @@ -288,7 +288,7 @@ struct brcm_pcie { static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->type == BCM7435 || pcie->type == BCM7425; + return pcie->model == BCM7435 || pcie->model == BCM7425; } /* @@ -852,7 +852,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * security considerations, and is not implemented in our modern * SoCs. */ - if (pcie->type != BCM7712) + if (pcie->model != BCM7712) set_bar(b++, &n, 0, 0, 0); resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -869,7 +869,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * That being said, each BARs size must still be a power of * two. */ - if (pcie->type == BCM7712) + if (pcie->model == BCM7712) set_bar(b++, &n, size, cpu_beg, pcie_beg); if (n > pcie->num_inbound) @@ -886,7 +886,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * that enables multiple memory controllers. As such, it can return * now w/o doing special configuration. */ - if (pcie->type == BCM7712) + if (pcie->model == BCM7712) return n; ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, @@ -1008,7 +1008,7 @@ static void set_inbound_win_registers(struct brcm_pcie *pcie, const struct rc_ba * 7712: * All of their BARs need to be set. */ - if (pcie->type == BCM7712) { + if (pcie->model == BCM7712) { /* BUS remap register settings */ reg_offset = brcm_ubus_reg_offset(i); tmp = lower_32_bits(cpu_addr) & ~0xfff; @@ -1036,7 +1036,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return ret; /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type == BCM2711) { + if (pcie->model == BCM2711) { ret = pcie->perst_set(pcie, 1); if (ret) { pcie->bridge_sw_init_set(pcie, 0); @@ -1067,9 +1067,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst = 0x1; /* 256 bytes */ - else if (pcie->type == BCM2711) + else if (pcie->model == BCM2711) burst = 0x0; /* 128 bytes */ - else if (pcie->type == BCM7278) + else if (pcie->model == BCM7278) burst = 0x3; /* 512 bytes */ else burst = 0x2; /* 512 bytes */ @@ -1666,7 +1666,7 @@ static const int pcie_offsets_bmips_7425[] = { static const struct pcie_cfg_data generic_cfg = { .offsets = pcie_offsets, - .type = GENERIC, + .model = GENERIC, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1674,7 +1674,7 @@ static const struct pcie_cfg_data generic_cfg = { static const struct pcie_cfg_data bcm7425_cfg = { .offsets = pcie_offsets_bmips_7425, - .type = BCM7425, + .model = BCM7425, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1682,7 +1682,7 @@ static const struct pcie_cfg_data bcm7425_cfg = { static const struct pcie_cfg_data bcm7435_cfg = { .offsets = pcie_offsets, - .type = BCM7435, + .model = BCM7435, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1690,7 +1690,7 @@ static const struct pcie_cfg_data bcm7435_cfg = { static const struct pcie_cfg_data bcm4908_cfg = { .offsets = pcie_offsets, - .type = BCM4908, + .model = BCM4908, .perst_set = brcm_pcie_perst_set_4908, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1706,7 +1706,7 @@ static const int pcie_offset_bcm7278[] = { static const struct pcie_cfg_data bcm7278_cfg = { .offsets = pcie_offset_bcm7278, - .type = BCM7278, + .model = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, .num_inbound = 3, @@ -1714,7 +1714,7 @@ static const struct pcie_cfg_data bcm7278_cfg = { static const struct pcie_cfg_data bcm2711_cfg = { .offsets = pcie_offsets, - .type = BCM2711, + .model = BCM2711, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, .num_inbound = 3, @@ -1722,7 +1722,7 @@ static const struct pcie_cfg_data bcm2711_cfg = { static const struct pcie_cfg_data bcm7216_cfg = { .offsets = pcie_offset_bcm7278, - .type = BCM7278, + .model = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, .has_phy = true, @@ -1779,7 +1779,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->dev = &pdev->dev; pcie->np = np; pcie->reg_offsets = data->offsets; - pcie->type = data->type; + pcie->model = data->model; pcie->perst_set = data->perst_set; pcie->bridge_sw_init_set = data->bridge_sw_init_set; pcie->has_phy = data->has_phy; @@ -1848,7 +1848,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { + if (pcie->model == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret = -ENODEV; goto fail; @@ -1863,7 +1863,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) } } - bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; + bridge->ops = pcie->model == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; bridge->sysdata = pcie; platform_set_drvdata(pdev, pcie);