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AJvYcCWc8ZH54xeY8GQAYUxeeTf6CpAljaDM3VUatiUgbGFKfz918d5K1NH7e0waZKiB5ekNmBMB9NQ2J4ZN63Nd6LK9i9GcUEzEfDYsh6OwK0hxDLRjK9M= X-Gm-Message-State: AOJu0Yww4NqPT1wOIG/P767WRrQOoUnqmbja+7oz0YUY0VSXOoA/VhXS d92FgiMmoxpacjEe/PpMZXUbW9NKJM7kFsPFLLT1L345RpGte5SR X-Google-Smtp-Source: AGHT+IG4RGm6UldBRPirm/sgg0RJFRpR7a2pTNHo9NF5qkkB4iyXZ5ybq2E6dEdqmje5bNCJc3Rb7w== X-Received: by 2002:a05:6830:391b:b0:703:b0e9:d951 with SMTP id 46e09a7af769-709008d0de4mr6872850a34.6.1721581751955; Sun, 21 Jul 2024 10:09:11 -0700 (PDT) Received: from kousik.local ([2405:201:c006:312d:f66f:2b12:abd:60ff]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70d285943e3sm417810b3a.213.2024.07.21.10.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jul 2024 10:09:11 -0700 (PDT) From: Kousik Sanagavarapu To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Nishanth Menon , Santosh Shilimkar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Kousik Sanagavarapu Subject: [PATCH 1/3] dt-bindings: timer: ti,davinci-timer: convert to dtschema Date: Sun, 21 Jul 2024 21:58:34 +0530 Message-ID: <20240721170840.15569-2-five231003@gmail.com> X-Mailer: git-send-email 2.45.2.827.g557ae147e6.dirty In-Reply-To: <20240721170840.15569-1-five231003@gmail.com> References: <20240721170840.15569-1-five231003@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240721_100913_327480_D07B64AC X-CRM114-Status: GOOD ( 17.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert txt binding of TI's DaVinci timer to dtschema to allow for validation. Signed-off-by: Kousik Sanagavarapu --- .../bindings/timer/ti,davinci-timer.txt | 37 ---------- .../bindings/timer/ti,davinci-timer.yaml | 68 +++++++++++++++++++ 2 files changed, 68 insertions(+), 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/ti,davinci-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/ti,davinci-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt deleted file mode 100644 index 29bf91ccf5b7..000000000000 --- a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt +++ /dev/null @@ -1,37 +0,0 @@ -* Device tree bindings for Texas Instruments DaVinci timer - -This document provides bindings for the 64-bit timer in the DaVinci -architecture devices. The timer can be configured as a general-purpose 64-bit -timer, dual general-purpose 32-bit timers. When configured as dual 32-bit -timers, each half can operate in conjunction (chain mode) or independently -(unchained mode) of each other. - -The timer is a free running up-counter and can generate interrupts when the -counter reaches preset counter values. - -Also see ../watchdog/davinci-wdt.txt for timers that are configurable as -watchdog timers. - -Required properties: - -- compatible : should be "ti,da830-timer". -- reg : specifies base physical address and count of the registers. -- interrupts : interrupts generated by the timer. -- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1", - "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6", - "cmpint7" ("cmpintX" may be omitted if not present in the - hardware). -- clocks : the clock feeding the timer clock. - -Example: - - clocksource: timer@20000 { - compatible = "ti,da830-timer"; - reg = <0x20000 0x1000>; - interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>, - <80>, <81>; - interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1", - "cmpint2", "cmpint3", "cmpint4", "cmpint5", - "cmpint6", "cmpint7"; - clocks = <&pll0_auxclk>; - }; diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.yaml b/Documentation/devicetree/bindings/timer/ti,davinci-timer.yaml new file mode 100644 index 000000000000..615ceb8f30af --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,davinci-timer.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/ti,davinci-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci Timer + +maintainers: + - Kousik Sanagavarapu + +description: | + + This is a 64-bit timer found on TI's DaVinci architecture devices. The timer + can be configured as a general-purpose 64-bit timer, dual general-purpose + 32-bit timers. When configured as dual 32-bit timers, each half can operate + in conjunction (chain mode) or independently (unchained mode) of each other. + + The timer is a free running up-counter and can generate interrupts when the + counter reaches preset counter values. + +properties: + compatible: + const: ti,da830-timer + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + + interrupt-names: + minItems: 2 + items: + - const: tint12 + - const: tint34 + - const: cmpint0 + - const: cmpint1 + - const: cmpint2 + - const: cmpint3 + - const: cmpint4 + - const: cmpint5 + - const: cmpint6 + - const: cmpint7 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + +additionalProperties: false + +examples: + - | + timer@20000 { + compatible = "ti,da830-timer"; + reg = <0x20000 0x1000>; + interrupts = <21>, <22>; + interrupt-names = "tint12", "tint34"; + clocks = <&pll0_auxclk>; + }; + +...