From patchwork Mon Jul 29 16:14:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13745381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E995C3DA61 for ; Mon, 29 Jul 2024 16:18:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UDYDx4DalxW/4nSqnb+RZjQRsE/6XRQnDD/JdL5aVm4=; b=qye7qIOqIBYCptLqy9V2WThq0o l3dzoM89dD+vYyiagYWiDaBhmzdbuQ4uakPy/WWi1Slw5BDRbpVbZepw/EdjXh4iKuHQo2vxULO9A hrgwl3DlIQJ9Rhpm+o/fXyFhJyf/F5USPRGbJNMXc6SyCvzVJfueMRw10zdQwJzwxT+1uFvG7mTi6 jLt/ezRl4FuykxAy3ullMK9+MW3m7FFYom8jpkZI8BvAF1RFrHB4cTtJqX8IvXYJFfgBsJscrgD9u uMbogoLVbpYg048AOy3NVMeY2CAsRav3BbzWaYkh3CFaNzCyHEMX/W1RxNb6MFRGF6i+Z1oVnqH/Z Tk0+0NWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYT4R-0000000Byz8-35pP; Mon, 29 Jul 2024 16:17:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYT1u-0000000ByMf-34qx for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 16:15:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8F5AB1007; Mon, 29 Jul 2024 09:15:44 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 271513F766; Mon, 29 Jul 2024 09:15:18 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER 06/11] aarch32: Implement cpu_init_arch() Date: Mon, 29 Jul 2024 17:14:56 +0100 Message-Id: <20240729161501.1806271-7-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240729161501.1806271-1-mark.rutland@arm.com> References: <20240729161501.1806271-1-mark.rutland@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240729_091522_844389_29963440 X-CRM114-Status: GOOD ( 10.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the boot-wrapper is entered at EL2/Hyp it does not initialise CNTFRQ, and in future it may need to initialize other CPU state regardless of the exeption level it was entered at. Use a common cpu_init_arch() function to initialize CPU state regardless of the exception level the boot-wrapper was entered at. For clarity cpu_init_secure_pl1() is renamed to cpu_init_monitor(), which better matches PSR_MON and will allow for the addition of cppu_init_hyp() and cpu_init_svc() in future. Signed-off-by: Mark Rutland Cc: Akos Denke Cc: Andre Przywara Cc: Luca Fancellu Cc: Marc Zyngier --- arch/aarch32/boot.S | 4 +++- arch/aarch32/init.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S index 43dce75..a6f0751 100644 --- a/arch/aarch32/boot.S +++ b/arch/aarch32/boot.S @@ -62,7 +62,7 @@ reset_at_mon: bl cpu_init_bootwrapper - bl cpu_init_secure_pl1 + bl cpu_init_arch bl gic_secure_init @@ -82,6 +82,8 @@ reset_at_hyp: bl cpu_init_bootwrapper + bl cpu_init_arch + b start_bootmethod err_invalid_id: diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c index e25f0c7..35da37c 100644 --- a/arch/aarch32/init.c +++ b/arch/aarch32/init.c @@ -29,7 +29,7 @@ void announce_arch(void) print_string("\r\n"); } -void cpu_init_secure_pl1(void) +static void cpu_init_monitor(void) { unsigned long scr = SCR_NS | SCR_HCE; unsigned long nsacr = NSACR_CP10 | NSACR_CP11; @@ -37,8 +37,6 @@ void cpu_init_secure_pl1(void) mcr(SCR, scr); mcr(NSACR, nsacr); - - mcr(CNTFRQ, COUNTER_FREQ); } #ifdef PSCI @@ -55,3 +53,11 @@ bool cpu_init_psci_arch(void) return true; } #endif + +void cpu_init_arch(void) +{ + if (read_cpsr_mode() == PSR_MON) + cpu_init_monitor(); + + mcr(CNTFRQ, COUNTER_FREQ); +}