From patchwork Tue Jul 30 09:13:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 13747083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2125DC3DA49 for ; Tue, 30 Jul 2024 09:14:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=a0FOV41hlSglKkyk1lbmBce/aSC9CS29cnin103FCZA=; b=dWz9PsQzKcTdebAiakyVvYUIEU ZKO/z5NGkTdU4wrcyHPSqkuXC0xyIV1bu0X0vCyHGJa75UcFWLY3N4TUAqGpAs9HyVu7MWe54vbIZ gIFzP5mOoZyG8QgWf+/c6qTRygO9tJtfntW7dXwgmZcN496ObuQaz06roaAYfh9HpQUj9xS1OnQxr /Nau3a6LVi44WsLKGydyuqp9UIXtt0DS8nP+vnMDr3tCFdUpQBqO+Lr+iBGNFTkUNQmaxar92DFbe 9IjihEqXNGSJnJpoGKC0zySxFv6GJzhGBUBsPYxRyaHGTQcysc1OwpsTWvLbOWrofwqmMDWu8bMin Y5oU58kA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYiwO-0000000ETLl-04Ad; Tue, 30 Jul 2024 09:14:44 +0000 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYivc-0000000ET69-2KU2 for linux-arm-kernel@lists.infradead.org; Tue, 30 Jul 2024 09:13:58 +0000 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-656d8b346d2so2517820a12.2 for ; Tue, 30 Jul 2024 02:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1722330836; x=1722935636; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a0FOV41hlSglKkyk1lbmBce/aSC9CS29cnin103FCZA=; b=d9YHRwhEGS66avV1GclWUQmyeLEDACnXJSV4ieI9xt8YHCprgWbPDJN2WmYdz/iSBS uyq+YQivS7o+hDge3pnBls3npKLVclnsPlYdjBgGTd9UY+wBdFsB9pWWtKHdQ6GrhVS5 TtFE7YIJqhQvrtfom83WI+hhUY9XACSHKj85zlHJw6IfyGMkzSHiXKKT1mqR7UdBO6Bj khQZJU3IFCJykoiGPK7VWT+yzsV0BVZFWr+Q9Z2mwNZaxkXjjSTccY74bo74rpIwTP/n qo/DuKVtZhe8NFKivylATcU/XAnlMqP3ZneNWrwJOm9Y7Be0eLXm5kjAbm1aaltrJbjH v7uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722330836; x=1722935636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a0FOV41hlSglKkyk1lbmBce/aSC9CS29cnin103FCZA=; b=TGGTohtYlSNMzN/B3DBIYmzMdOKnZB/VdcupTKFrttAscQKldIUSYpYssPnAtYsSdP aI5UqzLroMLNUBTcK6aokZGJ8U8FhqkumIVzKDx89myGc/pCDxE+gHySGBFO0GCcgcvW ebreOzJVs+4Uc0eIK0ZKSunWFfmyyCL+HchuqzA/Wc5BeBD8RY/M2XfyQVcCXdBUiOHF rppFaHpCPGL0aR2P7O/VDWq2Bggz0PD5EHXtmEuQbLkIVzpRLMISnRcrmKLAAK2ucZin ldKdMY6r4deWlbjldqgwfLSIKrbG6LIW5nuGt50qzZPnJbCxjzJm+jkRSgJ+Z+yR7Bgp uKHA== X-Forwarded-Encrypted: i=1; AJvYcCXFzVXl2ouVSYyyFgcKZz1FIVuvnOlug6POYHwUC8zvkpN7zjk6uzIVmCbyfgVarvVouO982uTHFV2K4r1JP++LtUjoCtpfwncg+SWb3yvlcxVDc9g= X-Gm-Message-State: AOJu0YyidD2tBVRX+ALyPgHNGuCF4kYp7jWrdRHwkgcoDRS/t658oa0u 1Jr82bLXIpSp/66+PhXLSOU2hbdEKTYbpT3zAOmqVUe0XmaUNyBM X-Google-Smtp-Source: AGHT+IFJZMmoK9n+EkJYAXejt/K7rDTAoEy+l/xOn0YQNuJIG8N02LJbOas6AZdB8iFFApnSMQG9ZA== X-Received: by 2002:a17:90a:468d:b0:2c9:7e80:6bc8 with SMTP id 98e67ed59e1d1-2cf7e71b37emr7818049a91.37.1722330835527; Tue, 30 Jul 2024 02:13:55 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.222]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cf28c565c9sm10023970a91.3.2024.07.30.02.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jul 2024 02:13:55 -0700 (PDT) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Anand Moon , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC Date: Tue, 30 Jul 2024 14:43:19 +0530 Message-ID: <20240730091322.5741-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730091322.5741-1-linux.amoon@gmail.com> References: <20240730091322.5741-1-linux.amoon@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240730_021356_617448_D65710E5 X-CRM114-Status: GOOD ( 14.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per Exynos 5422 user manual add missing cache information to the Exynos542x SoC. - Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available. - Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available. - The little (A7) cluster has 512 KB of unified L2 cache available. - The big (A15) cluster has 2 MB of unified L2 cache available. Features: - Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event. Signed-off-by: Anand Moon --- .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi index 412a0bb4b988..9b9b2bdfb522 100644 --- a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi @@ -59,6 +59,13 @@ cpu0: cpu@100 { reg = <0x100>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -72,6 +79,13 @@ cpu1: cpu@101 { reg = <0x101>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -85,6 +99,13 @@ cpu2: cpu@102 { reg = <0x102>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -98,6 +119,13 @@ cpu3: cpu@103 { reg = <0x103>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -111,6 +139,13 @@ cpu4: cpu@0 { reg = <0x0>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -124,6 +159,13 @@ cpu5: cpu@1 { reg = <0x1>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -137,6 +179,13 @@ cpu6: cpu@2 { reg = <0x2>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -150,12 +199,37 @@ cpu7: cpu@3 { reg = <0x3>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <310>; }; + + L2_a7: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; + + L2_a15: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; /* L2, 2M */ + cache-line-size = <64>; + cache-sets = <512>; + }; }; };