From patchwork Wed Jul 31 22:28:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13749302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DB4EC3DA7F for ; Wed, 31 Jul 2024 22:31:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BvkPsLOG5fUE2ytDC/96EogS/1H6a6HtgvVDjzytUG8=; b=rDKG8MgP57/3q3Gy0FAJpuhKYO PjOvnKR6Y69RiwG13S7GmOZZEUJ19sUEPBfDNU1rEEn1qYp31flD6YqMFyw9MbP0lBBhtc5bBb3H7 0VREMvI4IF+/UDLzVPtZ85LI/b9bz89HAvB9dd8n5DwjMlofdQMRW1AEbWsOD4B4g4KnaG/UXiTyu LqJeuP6mXbEn/WY/hi64169gBxkRnNEOqFOH11Oo5GJ4fCrzEJSB+GiTWjydMR+7AldRr5cCittpL KP3GYKXo2VMdLcvpVHdb4qfO/V9vXdQhA5K/Y4aWWYknp0cAAHAsmweAQsRMFi65FrbBG9T1SMcGm 7gKuQBDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZHqU-00000002iQP-2dYY; Wed, 31 Jul 2024 22:30:58 +0000 Received: from mail-qt1-x82a.google.com ([2607:f8b0:4864:20::82a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZHoI-00000002hSN-32eU for linux-arm-kernel@lists.infradead.org; Wed, 31 Jul 2024 22:28:44 +0000 Received: by mail-qt1-x82a.google.com with SMTP id d75a77b69052e-44ff7bdb5a6so31924601cf.3 for ; Wed, 31 Jul 2024 15:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1722464922; x=1723069722; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=BvkPsLOG5fUE2ytDC/96EogS/1H6a6HtgvVDjzytUG8=; b=AIx1MKwW/DiFdlSHg7hmWAXtn8vatFQ8h98IxA6DAE1QGFji+/TFJiVV+2tOxL4lNo JYT9flI6RFC3QadEi3WNbcnZtHLsYNO69SZW5zf7HYiX8DRgGyqAg/zLqSQAlx9hNDiz QW/HqONiWZVm9AJn/grDu3iAuauEIFcWubmsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722464922; x=1723069722; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=BvkPsLOG5fUE2ytDC/96EogS/1H6a6HtgvVDjzytUG8=; b=Xd8ki9U+KXpEyjOk6TMQfSNqpQZZFzBSeU1DNs6ysj5pPrLHbj9iTPuECGl+S3/n2+ QycajujwShaGXoBCxXZaESpByQ5umnhVB6gw1ffuyxqtC2CBzkU8s+4hfu3mMZJ5ky+C CXbxAU7LAngcLFDXTSaR3GFpCax7s2m8XNo+XmyuxNfBXk1WUsYTxkRX7pqjz1jkPIcQ DF1vwG6SjekDqF5fi6WhgooRABNKxkmjUnBx79Dh2yYlOVik2c8uZR3uansZY7DHR+EO HbEow4p56UHOpxcqQb4lbi8MRyzC5fMPCk/dmUpd9mHPQjumEx6TK2u0Wk+Ea6tqil1L EVVg== X-Forwarded-Encrypted: i=1; AJvYcCVdyJq6vH/4hTbN6pRjfMGdXjISAe1rryKUq6EInEzcG0MqnXyXOdBs34KvIbgwT13TSa5SJRCU64j465BsHXsZ@lists.infradead.org X-Gm-Message-State: AOJu0Yyh1K+r9MA/8YI74BPTjIHAm6cE4NzNgpG4McCfgOV0f2o74pqO rUA68UWk0ikBW3I4HlwbGuF2ZfxCBejbRQV1eUOw5PLU5c2VDtSLJ20D4nCS/g== X-Google-Smtp-Source: AGHT+IFBtq3zfvlVDpCsnHiydXJF3wP25FYPP/JkCKWE8phEA2Y4P9A5CFNfuo6bGZRLAirUY+0/bA== X-Received: by 2002:ac8:7f87:0:b0:447:e542:ab00 with SMTP id d75a77b69052e-451567a84b4mr8510471cf.50.1722464921783; Wed, 31 Jul 2024 15:28:41 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-44fe8416c80sm62359181cf.96.2024.07.31.15.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 15:28:41 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Philipp Zabel , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 05/12] PCI: brcmstb: Use swinit reset if available Date: Wed, 31 Jul 2024 18:28:19 -0400 Message-Id: <20240731222831.14895-6-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240731222831.14895-1-james.quinlan@broadcom.com> References: <20240731222831.14895-1-james.quinlan@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_152842_837503_0A6030E6 X-CRM114-Status: GOOD ( 13.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 7712 SOC adds a software init reset device for the PCIe HW. If found in the DT node, use it. Signed-off-by: Jim Quinlan Reviewed-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 4d68fe318178..948fd4d176bc 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -266,6 +266,7 @@ struct brcm_pcie { struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; + struct reset_control *swinit_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) if (IS_ERR(pcie->bridge_reset)) return PTR_ERR(pcie->bridge_reset); + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); + if (IS_ERR(pcie->swinit_reset)) + return PTR_ERR(pcie->swinit_reset); + ret = clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); pcie->bridge_sw_init_set(pcie, 0); + if (pcie->swinit_reset) { + ret = reset_control_assert(pcie->swinit_reset); + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) + goto clk_disable_unprepare; + + /* HW team recommends 1us for proper sync and propagation of reset */ + udelay(1); + + ret = reset_control_deassert(pcie->swinit_reset); + if (dev_err_probe(&pdev->dev, ret, + "could not de-assert reset 'swinit' after asserting\n")) + goto clk_disable_unprepare; + } + ret = reset_control_reset(pcie->rescal); if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) goto clk_disable_unprepare;