From patchwork Fri Aug 2 05:36:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 13751118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A159C52D71 for ; Fri, 2 Aug 2024 05:38:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xlZ4/Kw11xpyrMXD0cAsdFdsF3dDK1F5MYgwiSI6304=; b=S34evxiA2tLj5w/EWbNgimLJg+ Gt9mvyjKmoWNgApmZ9fcgmDuHyWDPTc1gijfmyHfqRix1/t+HEbfNFUxAOke33J4lZzuQZCqk4b4x 0SbdM+CNaOdKq5oRCG+QH6ty0+cmj6ANbqzSt0Ea7sTZa0VzL9LkpqQBfddIGMUdjAxVnMkoZJOdy IjZ8K4HrUjTH5wSbd7vxk3/7xew/BtVvGhe+IK5HzyM9FpBM3xJrpwMnjdbw/dk07ue1KdL67G4dT VtWEoW/RN7YgLxv/Lj4LK3pIXMQEWdnm5vLXXRECily59oz6ubqp0+lso5ghaN7ubfUa+8WGstE/u 4ZMN2rqg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZkzZ-00000007i91-1Ybs; Fri, 02 Aug 2024 05:38:17 +0000 Received: from pi.codeconstruct.com.au ([203.29.241.158] helo=codeconstruct.com.au) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZkyB-00000007hpa-1uaD for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2024 05:36:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1722577009; bh=xlZ4/Kw11xpyrMXD0cAsdFdsF3dDK1F5MYgwiSI6304=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ILzoFj4JHHtHcpMCOKJ6MMAerPlbAY5PRWfKzguT3wZFVbawVINU/c8u8K+tKi9LD abfvrYUJKiZZdj/V4Qb6HljDj5VhanCYBR38ngzyefmHQJuHpQYa5nLmDPsC1nMeJ0 +b3chIs0EJleJtkJOiHXqjHGWfn/AmskmYg8joBeaNMSgCC+Gp53s6WH5lua+P4Rvq t4HSP7mbvlvWzfdnrlz1jpGtot81TM8JZZ7rgZHlawSbNTjRXICA/rdapC55aH1diD fVWcMQv0wG8bT/+e1jd3oRb8G4uJ6AYI0KFmbLmxOpd5X4Yp6faA1ROFLOWW1dMuB6 BbfZaFWMtVigA== Received: from [127.0.1.1] (ppp118-210-29-70.adl-adc-lon-bras31.tpg.internode.on.net [118.210.29.70]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id 0888C66E06; Fri, 2 Aug 2024 13:36:48 +0800 (AWST) From: Andrew Jeffery Date: Fri, 02 Aug 2024 15:06:31 +0930 Subject: [PATCH 2/2] dt-bindings: misc: aspeed,ast2400-cvic: Convert to DT schema MIME-Version: 1.0 Message-Id: <20240802-dt-warnings-irq-aspeed-dt-schema-v1-2-8cd4266d2094@codeconstruct.com.au> References: <20240802-dt-warnings-irq-aspeed-dt-schema-v1-0-8cd4266d2094@codeconstruct.com.au> In-Reply-To: <20240802-dt-warnings-irq-aspeed-dt-schema-v1-0-8cd4266d2094@codeconstruct.com.au> To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org X-Mailer: b4 0.14.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240801_223651_985288_2026D7DD X-CRM114-Status: GOOD ( 18.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Address warnings such as: arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dtb: interrupt-controller@1e6c0080: 'valid-sources' does not match any of the regexes: 'pinctrl-[0-9]+' and arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dtb: /ahb/copro-interrupt-controller@1e6c2000: failed to match any schema with compatible: ['aspeed,ast2400-cvic', 'aspeed-cvic'] Note that the conversion to DT schema causes some further warnings to be emitted, because the Aspeed devicetrees are not in great shape. These new warnings are resolved in a separate series: https://lore.kernel.org/lkml/20240802-dt-warnings-bmc-dts-cleanups-v1-0-1cb1378e5fcd@codeconstruct.com.au/ Signed-off-by: Andrew Jeffery --- .../bindings/misc/aspeed,ast2400-cvic.yaml | 60 ++++++++++++++++++++++ .../devicetree/bindings/misc/aspeed,cvic.txt | 35 ------------- 2 files changed, 60 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml b/Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml new file mode 100644 index 000000000000..3c85b4924c05 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/aspeed,ast2400-cvic.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Coprocessor Vectored Interrupt Controller + +maintainers: + - Andrew Jeffery + +description: + The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts + to the ColdFire coprocessor. It's not a normal interrupt controller and it + would be rather inconvenient to create an interrupt tree for it, as it + somewhat shares some of the same sources as the main ARM interrupt controller + but with different numbers. + + The AST2500 also supports a software generated interrupt. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-cvic + - aspeed,ast2500-cvic + - const: aspeed,cvic + + reg: + maxItems: 1 + + valid-sources: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + One cell, bitmap of support sources for the implementation. + + copro-sw-interrupts: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + A list of interrupt numbers that can be used as software interrupts from + the ARM to the coprocessor. + +required: + - compatible + - reg + - valid-sources + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +additionalProperties: false + +examples: + - | + interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2500-cvic", "aspeed,cvic"; + reg = <0x1e6c2000 0x80>; + valid-sources = <0xffffffff>; + copro-sw-interrupts = <1>; + }; diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt deleted file mode 100644 index d62c783d1d5e..000000000000 --- a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt +++ /dev/null @@ -1,35 +0,0 @@ -* ASPEED AST2400 and AST2500 coprocessor interrupt controller - -This file describes the bindings for the interrupt controller present -in the AST2400 and AST2500 BMC SoCs which provides interrupt to the -ColdFire coprocessor. - -It is not a normal interrupt controller and it would be rather -inconvenient to create an interrupt tree for it as it somewhat shares -some of the same sources as the main ARM interrupt controller but with -different numbers. - -The AST2500 supports a SW generated interrupt - -Required properties: -- reg: address and length of the register for the device. -- compatible: "aspeed,cvic" and one of: - "aspeed,ast2400-cvic" - or - "aspeed,ast2500-cvic" - -- valid-sources: One cell, bitmap of supported sources for the implementation - -Optional properties; -- copro-sw-interrupts: List of interrupt numbers that can be used as - SW interrupts from the ARM to the coprocessor. - (AST2500 only) - -Example: - - cvic: copro-interrupt-controller@1e6c2000 { - compatible = "aspeed,ast2500-cvic"; - valid-sources = <0xffffffff>; - copro-sw-interrupts = <1>; - reg = <0x1e6c2000 0x80>; - };