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AJvYcCWc8ilt495e08X+VDIzLvXnIrWhumaQtgN3bjfLZSAV0ESLNYHSnPnBxjDYz3WfXZ2EdZOeC7MhIvAlqULUIS82q6yF6Z7Zl3jUEYwpxVXNHkVy/Js= X-Gm-Message-State: AOJu0YwaJvQLmP3uA7RRD92p1sk259EMkmI1Xx07EFtjrL+GvFmtOPQ6 uZ95E2dK0WXW5Pos54N3PenYSD/1zX5nlN4BxQYS12tFb3Tz3Oo0jY8wrdfqOLFnSrmBuHlGyH8 = X-Google-Smtp-Source: AGHT+IGLq0mErGqzzVN2fu1NHv5FwQg+WZUq33b12gl6nvqOLVq6lohDfRmMscu6BBut3VG69qGzww== X-Received: by 2002:a17:903:182:b0:1ff:5135:130d with SMTP id d9443c01a7336-1ff57261cc7mr32752225ad.16.1722582595790; Fri, 02 Aug 2024 00:09:55 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:f2e4:75b7:52fc:71cc]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff58f19e15sm10228345ad.40.2024.08.02.00.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Aug 2024 00:09:55 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: mediatek: mt8195: Correct clock order for dp_intf* Date: Fri, 2 Aug 2024 15:09:50 +0800 Message-ID: <20240802070951.1086616-1-wenst@chromium.org> X-Mailer: git-send-email 2.46.0.rc2.264.g509ed76dc8-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_001004_155708_59451A88 X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The clocks for dp_intf* device nodes are given in the wrong order, causing the binding validation to fail. Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes") Signed-off-by: Chen-Yu Tsai Reviewed-by: Nícolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 989e8ac545ac..e89ba384c4aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3252,10 +3252,10 @@ dp_intf0: dp-intf@1c015000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c015000 0 0x1000>; interrupts = ; - clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, - <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&vdosys0 CLK_VDO0_DP_INTF0>, <&apmixedsys CLK_APMIXED_TVDPLL1>; - clock-names = "engine", "pixel", "pll"; + clock-names = "pixel", "engine", "pll"; status = "disabled"; }; @@ -3522,10 +3522,10 @@ dp_intf1: dp-intf@1c113000 { reg = <0 0x1c113000 0 0x1000>; interrupts = ; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, - <&vdosys1 CLK_VDO1_DPINTF>, + clocks = <&vdosys1 CLK_VDO1_DPINTF>, + <&vdosys1 CLK_VDO1_DP_INTF0_MM>, <&apmixedsys CLK_APMIXED_TVDPLL2>; - clock-names = "engine", "pixel", "pll"; + clock-names = "pixel", "engine", "pll"; status = "disabled"; };