From patchwork Fri Aug 2 09:05:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 13751294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7791C3DA4A for ; Fri, 2 Aug 2024 09:08:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RO+oSewRimrjUZUhPKmlHboJgrwIcYYYC6bfDV/ik1Q=; b=bupPaX+23qEalFNUaOd2tjkvoZ xBk0+kcDq9gm70YMVaTSvb1nteCblzt9NkhjHlgsXm6Pwi9koTP6su/PdK3/C+KPnNeRDeB04khnW tlquDp90DhGwRG3kEk8WrmyYKISXKN0nRcsGMZJnCu9sBvQ8BiuSLAyJN7LsDswmvhQHcizrn9m4D ftLvN/ka7eSpa8DvmotuRwuaH6cJ5B42bc4JcYkafdVOZJs387f+ILgPSW7v70ORFyESW3SGh5BqY Bj2lI6msAuCa/R/F20bvBPmgmtpV06R9tNZzUfr41k/oEEIJxDTb0mUHJCWhNOhHBy19A18oqBdsu Xz9M9F3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZoGW-00000008CYY-0pWX; Fri, 02 Aug 2024 09:08:00 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZoEe-00000008Box-2H7u for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2024 09:06:05 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 2 Aug 2024 17:05:51 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 2 Aug 2024 17:05:51 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 2/9] dt-bindings: reset: ast2700: Add ASPEED AST27xx Reset schema Date: Fri, 2 Aug 2024 17:05:37 +0800 Message-ID: <20240802090544.2741206-4-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240802090544.2741206-1-kevin_chen@aspeedtech.com> References: <20240802090544.2741206-1-kevin_chen@aspeedtech.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_020604_615614_DECCEE0F X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Reset schema for AST2700. Signed-off-by: Kevin Chen --- .../dt-bindings/reset/aspeed,ast2700-reset.h | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h diff --git a/include/dt-bindings/reset/aspeed,ast2700-reset.h b/include/dt-bindings/reset/aspeed,ast2700-reset.h new file mode 100644 index 000000000000..c75653c1bbf3 --- /dev/null +++ b/include/dt-bindings/reset/aspeed,ast2700-reset.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Device Tree binding constants for AST2700 reset controller. + * + * Copyright (c) 2023 Aspeed Technology Inc. + */ + +#ifndef _MACH_ASPEED_AST2700_RESET_H_ +#define _MACH_ASPEED_AST2700_RESET_H_ + +/* SOC0 */ +#define SCU0_RESET_SDRAM (0) +#define SCU0_RESET_DDRPHY (1) +#define SCU0_RESET_RSA (2) +#define SCU0_RESET_SHA3 (3) +#define SCU0_RESET_HACE (4) +#define SCU0_RESET_SOC (5) +#define SCU0_RESET_VIDEO (6) +#define SCU0_RESET_2D (7) +#define SCU0_RESET_PCIS (8) +#define SCU0_RESET_RVAS0 (9) +#define SCU0_RESET_RVAS1 (10) +#define SCU0_RESET_SM3 (11) +#define SCU0_RESET_SM4 (12) +#define SCU0_RESET_CRT0 (13) +#define SCU0_RESET_ECC (14) +#define SCU0_RESET_DP_PCI (15) +#define SCU0_RESET_UFS (16) +#define SCU0_RESET_EMMC (17) +#define SCU0_RESET_PCIE1RST (18) +#define SCU0_RESET_PCIE1RSTOE (19) +#define SCU0_RESET_PCIE0RST (20) +#define SCU0_RESET_PCIE0RSTOE (21) +#define SCU0_RESET_JTAG (22) +#define SCU0_RESET_MCTP0 (23) +#define SCU0_RESET_MCTP1 (24) +#define SCU0_RESET_XDMA0 (25) +#define SCU0_RESET_XDMA1 (26) +#define SCU0_RESET_H2X1 (27) +#define SCU0_RESET_DP (28) +#define SCU0_RESET_DP_MCU (29) +#define SCU0_RESET_SSP (30) +#define SCU0_RESET_H2X0 (31) +#define SCU0_RESET_PORTA_VHUB1 (32) +#define SCU0_RESET_PORTA_PHY3 (33) +#define SCU0_RESET_PORTA_XHCI (34) +#define SCU0_RESET_PORTB_VHUB1 (35) +#define SCU0_RESET_PORTB_PHY3 (36) +#define SCU0_RESET_PORTB_XHCI (37) +#define SCU0_RESET_PORTA_EHCI (38) +#define SCU0_RESET_PORTA_VHUB0 (38) +#define SCU0_RESET_PORTB_EHCI (39) +#define SCU0_RESET_PORTB_VHUB0 (39) +#define SCU0_RESET_UHCI (40) +#define SCU0_RESET_TSP (41) +#define SCU0_RESET_E2M0 (42) +#define SCU0_RESET_E2M1 (43) +#define SCU0_RESET_VLINK (44) + +#define SOC0_RESET_NUMS (SCU0_RESET_VLINK + 1) + +/* SOC1 */ +#define SCU1_RESET_LPC0 (0) +#define SCU1_RESET_LPC1 (1) +#define SCU1_RESET_MII (2) +#define SCU1_RESET_PECI (3) +#define SCU1_RESET_PWM (4) +#define SCU1_RESET_MAC0 (5) +#define SCU1_RESET_MAC1 (6) +#define SCU1_RESET_MAC2 (7) +#define SCU1_RESET_ADC (8) +#define SCU1_RESET_SD (9) +#define SCU1_RESET_ESPI0 (10) +#define SCU1_RESET_ESPI1 (11) +#define SCU1_RESET_JTAG1 (12) +#define SCU1_RESET_SPI0 (13) +#define SCU1_RESET_SPI1 (14) +#define SCU1_RESET_SPI2 (15) +#define SCU1_RESET_I3C0 (16) +#define SCU1_RESET_I3C1 (17) +#define SCU1_RESET_I3C2 (18) +#define SCU1_RESET_I3C3 (19) +#define SCU1_RESET_I3C4 (20) +#define SCU1_RESET_I3C5 (21) +#define SCU1_RESET_I3C6 (22) +#define SCU1_RESET_I3C7 (23) +#define SCU1_RESET_I3C8 (24) +#define SCU1_RESET_I3C9 (25) +#define SCU1_RESET_I3C10 (26) +#define SCU1_RESET_I3C11 (27) +#define SCU1_RESET_I3C12 (28) +#define SCU1_RESET_I3C13 (29) +#define SCU1_RESET_I3C14 (30) +#define SCU1_RESET_I3C15 (31) +#define SCU1_RESET_I3C15 (31) +#define SCU1_RESET_MCU0 (32) +#define SCU1_RESET_MCU1 (33) +#define SCU1_RESET_H2A_SPI1 (34) +#define SCU1_RESET_H2A_SPI2 (35) +#define SCU1_RESET_UART0 (36) +#define SCU1_RESET_UART1 (37) +#define SCU1_RESET_UART2 (38) +#define SCU1_RESET_UART3 (39) +#define SCU1_RESET_I2C_FILTER (40) +#define SCU1_RESET_CALIPTRA (41) +#define SCU1_RESET_XDMA (42) +/* reserved 43 */ +#define SCU1_RESET_FSI (44) +#define SCU1_RESET_CAN (45) +#define SCU1_RESET_MCTP (46) +#define SCU1_RESET_I2C (47) +#define SCU1_RESET_UART6 (48) +#define SCU1_RESET_UART7 (49) +#define SCU1_RESET_UART8 (50) +#define SCU1_RESET_UART9 (51) +#define SCU1_RESET_LTPI (52) +#define SCU1_RESET_VGAL (53) +#define SCU1_RESET_LTPI1 (54) +#define SCU1_RESET_ACE (55) +#define SCU1_RESET_E2M (56) +#define SCU1_RESET_UHCI (57) +#define SCU1_RESET_PORTC_EHCI (58) +#define SCU1_RESET_PORTC_VHUB (59) +#define SCU1_RESET_PORTD_EHCI (60) +#define SCU1_RESET_PORTD_VHUB (61) +#define SCU1_RESET_H2X (62) +#define SCU1_RESET_I3CDMA (63) +#define SCU1_RESET_PCIE2RST (64) + +#define SOC1_RESET_NUMS (SCU1_RESET_PCIE2RST + 1) + +#endif /* _MACH_ASPEED_AST2700_RESET_H_ */