From patchwork Wed Aug 7 16:41:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13756510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 867FEC52D73 for ; Wed, 7 Aug 2024 16:47:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mcrqh1xkaoLHfHITf2J9tJlA+5CJPtjmIAWfoGtmICg=; b=3OnS6/caIagCFk7kGg6atffyk+ I9f1OSHFKPFFVhajvtV8yfltVvrHGVvcmra1bRHeLSr9G0KntYV4ZaG96Cg8jOEKc2ZQmV8rK5xLP 9a0qbvtGkiz2k5WkqJFRIc1HyZXXZJL3KyOp7h0hSx53MH/YIieS4udXEfG+0P01b1IMOXIUHUp4p BqGPZFGCjge6TPR/M1yh0E0DqJUte1poMUCEpRspJJizG+syyu49VFoBm8uD+96O5AlUly2FXCVEB 2x9sFx9JI8gmeRbATedxNzAPVK3xDGe44dFUG6yt+q0ouxoTFWhPk0yZFwCa/KYmJLoZDR34EuYGK 35JlsZJw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbjoZ-00000005jN2-19aK; Wed, 07 Aug 2024 16:47:07 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbjjC-00000005iM3-14tw for linux-arm-kernel@lists.infradead.org; Wed, 07 Aug 2024 16:41:35 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id BF739611F9; Wed, 7 Aug 2024 16:41:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 27C85C4AF0E; Wed, 7 Aug 2024 16:41:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723048893; bh=Iib8j7kLFuTt0G9VpmR7ZC6LE2Yk3Zh0TL0yRAGzgxQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B8EoAMpw6xqgNBVLV7Oivpz4X+5ItbTcgQOYkGvbjE1c9loKPoCruEPjTW/nHa6OF NyxqHrDmDDl0HZUWB/GG/X2qoXS4S6ruIo0ZdpMP1YI7HCW0do8fwYsQZhnv3fugmZ mnov6zwSc39pzU+wzASWeaBAZmJE7YsQbh3smk+o+2RdBGWaXqjhHCT01yyldKbKWq SDngJwfjq9LFrV+NW52fJmZiY6R1MCCPuzk31AkmAII/EmiKBWZzxHJiInf4WneseI cxSdZfB5eqwLJ5OAdVXFkd5ehaYNqMGzUtBNQnf2lCDsRefCkH4odZGekEwElbUP5U yhVoKZVA7q4IA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= , stable+noautosel@kernel.org Subject: [PATCH v2 09/12] irqchip/armada-370-xp: Fix reenabling last per-CPU interrupt Date: Wed, 7 Aug 2024 18:41:01 +0200 Message-ID: <20240807164104.4140-10-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240807164104.4140-1-kabel@kernel.org> References: <20240807164104.4140-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_094134_413456_784D88D6 X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The number of per-CPU interrupts is 29 (0 to 28). This is described by the constant MPIC_MAX_PER_CPU_IRQS, set to 28 (the maximum per-CPU interrupt). Commit 0fa4ce746d1d ("irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time") used the constant incorrectly in the for-loop, it used the operator < instead of <=, causing it to iterate only the first 28 interrupts (0 to 27), ignoring the last, 28th, per-CPU interrupt. To avoid this kind of confusions, fix this issue by renaming the constant to MPIC_PER_CPU_IRQS_NR and set it to 29, the number of per-CPU IRQs. Update its use in mpic_is_percpu_irq() accordingly. Cc: # The 29th interrupt is not used in any device-tree Fixes: 0fa4ce746d1d ("irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time") Signed-off-by: Marek Behún --- Thomas, I have added the stable+noautosel Cc so that this patch won't be autoselected for stable releases, as described in Documentation/process/stable-kernel-rules.rst. This way I can keep the Fixes tag. --- drivers/irqchip/irq-armada-370-xp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index f8658a232f21..83afc3a27812 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -133,7 +133,7 @@ #define MPIC_INT_FABRIC_MASK 0x54 #define MPIC_INT_CAUSE_PERF(cpu) BIT(cpu) -#define MPIC_MAX_PER_CPU_IRQS 28 +#define MPIC_PER_CPU_IRQS_NR 29 /* IPI and MSI interrupt definitions for IPI platforms */ #define IPI_DOORBELL_NR 8 @@ -202,7 +202,7 @@ static inline bool mpic_is_ipi_available(struct mpic *mpic) static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq) { - return hwirq <= MPIC_MAX_PER_CPU_IRQS; + return hwirq < MPIC_PER_CPU_IRQS_NR; } /* @@ -545,7 +545,7 @@ static void mpic_smp_cpu_init(struct mpic *mpic) static void mpic_reenable_percpu(struct mpic *mpic) { /* Re-enable per-CPU interrupts that were enabled before suspend */ - for (irq_hw_number_t i = 0; i < MPIC_MAX_PER_CPU_IRQS; i++) { + for (irq_hw_number_t i = 0; i < MPIC_PER_CPU_IRQS_NR; i++) { unsigned int virq = irq_linear_revmap(mpic->domain, i); struct irq_data *d;