From patchwork Wed Aug 7 16:41:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13756512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32EF2C52D73 for ; Wed, 7 Aug 2024 16:48:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=zgFxP5diYWklh2PyayVRR1MAcAM9c31zNKxHTmjFm9o=; b=Ytx0EtZneks9NMbjETeJfzKmk5 PEa4HPUPrjHLuWGuaS5xrvwqVPMtRj4+yDSOTKfbxIdCnKdWy7MJTDkNAnCoh6hv2rTfI34tshD3z SXho9QLqYRoxTMcYoUpFZODIILBc7XIeYjoi7tjMv8Pa4chNHvXmEUwu3CU4LuTeR1ZP59UyVAIBO c8PdiQUHwjrtGfYYynUId2Q1XZonjTCVfmLU6mckfny8OtvgzlmSPlUjT8mUO+RMx1lo/UOxUTzye 4cnY4NNRfx7lpTOqMxTxd1HO6KmG+yVJgcHgi2XS4CJVgz6vH4Ml6v0jyJB3KR/R6AF0FO4KVyP63 SaVXik0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbjpa-00000005jZU-2qsU; Wed, 07 Aug 2024 16:48:10 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbjjJ-00000005iNk-1PVF for linux-arm-kernel@lists.infradead.org; Wed, 07 Aug 2024 16:41:42 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 9B489CE1152; Wed, 7 Aug 2024 16:41:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7E961C4AF0E; Wed, 7 Aug 2024 16:41:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723048898; bh=QrfXdjkPxDu2eJziaOP1zH8ANrG9tAjs3ToPCDrZHDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZZ4YWO0SNZKJ1bxGwXkGY/NNUVT7MV1edxYcSN7Q0RyRiQRtzAo7JybvtjeUFo9kh 8itG+2qQyMvNq+q0outt3/uu82EKBs/pnM3m/+5c3K/eoGGIU2FkNJ4P/SvKCXxgTl xuR26RiOc3hzCB3N8H6QJ2lZVLtxYmpn6HIWiUicL1tovhFv2krBnb9vao/27RgJHl EQvOX9P2agbmV46dQ9eYszArK9y+EjoMD/Owrco4hZD/R6Q2WdRYbFga2m5IcGY3pG MMpwFD4GdBkhbD5g5g8lsVeB01vaSnbKKFOreOfroBd4mvOws+RAvQzCU/aDncapDS n146C02GAt2pg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH v2 11/12] irqchip/armada-370-xp: Allow mapping only per-CPU interrupts Date: Wed, 7 Aug 2024 18:41:03 +0200 Message-ID: <20240807164104.4140-12-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240807164104.4140-1-kabel@kernel.org> References: <20240807164104.4140-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_094141_594559_D916BE96 X-CRM114-Status: GOOD ( 14.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On platforms where MPIC is not the top-level interrupt controller the driver currently only supports handling of the per-CPU interrupts (the first 29 interrupts). This is obvious from the code of mpic_handle_cascade_irq(), which reads only one cause register. Bound the number of available interrupts in the IRQ domain to 29 for these platforms. The corresponding device-trees refer only to per-CPU interrupts via MPIC, the other interrupts are referred to via GIC. Signed-off-by: Marek Behún --- drivers/irqchip/irq-armada-370-xp.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 36d1bac8a99f..4f3f99af12b2 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -848,6 +848,19 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par for (irq_hw_number_t i = 0; i < nr_irqs; i++) writel(i, mpic->base + MPIC_INT_CLEAR_ENABLE); + /* + * Initialize mpic->parent_irq before calling any other functions, since + * it is used to distinguish between IPI and non-IPI platforms. + */ + mpic->parent_irq = irq_of_parse_and_map(node, 0); + + /* + * On non-IPI platforms the driver currently supports only the per-CPU + * interrupts (the first 29 interrupts). See mpic_handle_cascade_irq(). + */ + if (!mpic_is_ipi_available(mpic)) + nr_irqs = MPIC_PER_CPU_IRQS_NR; + mpic->domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, mpic); if (!mpic->domain) { pr_err("%pOF: Unable to add IRQ domain\n", node); @@ -856,12 +869,6 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par irq_domain_update_bus_token(mpic->domain, DOMAIN_BUS_WIRED); - /* - * Initialize mpic->parent_irq before calling any other functions, since - * it is used to distinguish between IPI and non-IPI platforms. - */ - mpic->parent_irq = irq_of_parse_and_map(node, 0); - /* Setup for the boot CPU */ mpic_perf_init(mpic); mpic_smp_cpu_init(mpic);