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Thu, 8 Aug 2024 14:04:13 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 Aug 2024 07:04:09 -0700 From: Luo Jie Date: Thu, 8 Aug 2024 22:03:14 +0800 Subject: [PATCH 3/4] arm64: defconfig: Enable Qualcomm IPQ common PLL clock controller MIME-Version: 1.0 Message-ID: <20240808-qcom_ipq_cmnpll-v1-3-b0631dcbf785@quicinc.com> References: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> In-Reply-To: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723125835; l=686; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=3WH0aRycawtTd+hwuDHZymvMm+tSFS7uVvav4SszNxo=; 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Signed-off-by: Luo Jie --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 01dd286ba7ef..1bc7bd86e589 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y