From patchwork Thu Aug 8 07:10:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 13757010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9ADC6C52D73 for ; Thu, 8 Aug 2024 07:14:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FedGXBbxZS85QIbKrUIqDEcBbjDFn92tK2MtTO/ElYU=; b=HCDPM+u1arfiISdUeUvMz4HrnK tdUYTPyqEt2YUdS07vyUkPRin8QrC9o3QYw478WHO8VCwR+nNsDuDUlvBYVjFl7wrGAcUuYkc0KHs FiB0JX8SOKeU5Wbhx8dVcSrBM+VmcW++SZViTz71G8aaq5Mda/tuSuI6s5ZnkXm5OQdg0M1TJt9Wk L5DnQKZGISiUfp2m8tB0sHMW6UTTxdv7JssspOGB+V/9+Ds8uBbCkjVV61mnEGgsf2TSLcRxlwxMJ zKpI7/VRfxh35JgZq1WRmBslnAUTgRqC3+e8qNYKu+jI81EwliAlM53d/4TUz3jFKuK3vPS0bSYPk AL1ZIlew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbxLU-00000007KzK-1UeZ; Thu, 08 Aug 2024 07:14:00 +0000 Received: from relay6-d.mail.gandi.net ([2001:4b98:dc4:8::226]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbxJH-00000007K1L-0iaI for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2024 07:11:46 +0000 Received: by mail.gandi.net (Postfix) with ESMTPA id 0057EC000C; Thu, 8 Aug 2024 07:11:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1723101101; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FedGXBbxZS85QIbKrUIqDEcBbjDFn92tK2MtTO/ElYU=; b=YIyD+2Xy+fDnZkHlX93E7CsEPEw+MB9zrg4gL4VhwDukhyUr9STvaatDp7737M/AAn2OgW 0oNgsZ0mDsRGa8lnmbydvTFD0GJ8snXbabyBgXMy1Q7YKDe5gLeoRJDXM0ivbscbp5O01+ 8S1kLvaU3CEJIKsUhELQBgvsJi5hl3keUEpQ4WMXTNctFmUpse5YZVtCX1FxcTpnj9sUq0 XJ7VUMxlXDPcAybDmS77e55itJM5sVZ0WU1XZH/TH1PMT+RXqoP87kUYSpJEB2W4WYWiI3 b2sl6NZcnwnMHy3niCVJIM1gJ5A9+ctMsdwXcuGtcgUMi9ZpW/C1S169lz27ag== From: Herve Codina To: Herve Codina , Christophe Leroy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Qiang Zhao , Li Yang , Mark Brown Cc: linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni Subject: [PATCH v2 04/36] soc: fsl: cpm1: tsa: Use BIT(), GENMASK() and FIELD_PREP() macros Date: Thu, 8 Aug 2024 09:10:57 +0200 Message-ID: <20240808071132.149251-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240808071132.149251-1-herve.codina@bootlin.com> References: <20240808071132.149251-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: herve.codina@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240808_001143_520032_6AB307D9 X-CRM114-Status: UNSURE ( 9.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org checkpatch.pl signals the following improvement for tsa.c CHECK: Prefer using the BIT macro Follow its suggestion and convert the code to BIT() and related macros. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/tsa.c | 127 +++++++++++++++++++++------------------ 1 file changed, 68 insertions(+), 59 deletions(-) diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c index 53968ea84c88..dc4dda17dab8 100644 --- a/drivers/soc/fsl/qe/tsa.c +++ b/drivers/soc/fsl/qe/tsa.c @@ -9,6 +9,7 @@ #include "tsa.h" #include +#include #include #include #include @@ -19,47 +20,52 @@ /* TSA SI RAM routing tables entry */ -#define TSA_SIRAM_ENTRY_LAST (1 << 16) -#define TSA_SIRAM_ENTRY_BYTE (1 << 17) -#define TSA_SIRAM_ENTRY_CNT(x) (((x) & 0x0f) << 18) -#define TSA_SIRAM_ENTRY_CSEL_MASK (0x7 << 22) -#define TSA_SIRAM_ENTRY_CSEL_NU (0x0 << 22) -#define TSA_SIRAM_ENTRY_CSEL_SCC2 (0x2 << 22) -#define TSA_SIRAM_ENTRY_CSEL_SCC3 (0x3 << 22) -#define TSA_SIRAM_ENTRY_CSEL_SCC4 (0x4 << 22) -#define TSA_SIRAM_ENTRY_CSEL_SMC1 (0x5 << 22) -#define TSA_SIRAM_ENTRY_CSEL_SMC2 (0x6 << 22) +#define TSA_SIRAM_ENTRY_LAST BIT(16) +#define TSA_SIRAM_ENTRY_BYTE BIT(17) +#define TSA_SIRAM_ENTRY_CNT_MASK GENMASK(21, 18) +#define TSA_SIRAM_ENTRY_CNT(x) FIELD_PREP(TSA_SIRAM_ENTRY_CNT_MASK, x) +#define TSA_SIRAM_ENTRY_CSEL_MASK GENMASK(24, 22) +#define TSA_SIRAM_ENTRY_CSEL_NU FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x0) +#define TSA_SIRAM_ENTRY_CSEL_SCC2 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x2) +#define TSA_SIRAM_ENTRY_CSEL_SCC3 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x3) +#define TSA_SIRAM_ENTRY_CSEL_SCC4 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x4) +#define TSA_SIRAM_ENTRY_CSEL_SMC1 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x5) +#define TSA_SIRAM_ENTRY_CSEL_SMC2 FIELD_PREP_CONST(TSA_SIRAM_ENTRY_CSEL_MASK, 0x6) /* SI mode register (32 bits) */ #define TSA_SIMODE 0x00 -#define TSA_SIMODE_SMC2 0x80000000 -#define TSA_SIMODE_SMC1 0x00008000 -#define TSA_SIMODE_TDMA(x) ((x) << 0) -#define TSA_SIMODE_TDMB(x) ((x) << 16) -#define TSA_SIMODE_TDM_MASK 0x0fff -#define TSA_SIMODE_TDM_SDM_MASK 0x0c00 -#define TSA_SIMODE_TDM_SDM_NORM 0x0000 -#define TSA_SIMODE_TDM_SDM_ECHO 0x0400 -#define TSA_SIMODE_TDM_SDM_INTL_LOOP 0x0800 -#define TSA_SIMODE_TDM_SDM_LOOP_CTRL 0x0c00 -#define TSA_SIMODE_TDM_RFSD(x) ((x) << 8) -#define TSA_SIMODE_TDM_DSC 0x0080 -#define TSA_SIMODE_TDM_CRT 0x0040 -#define TSA_SIMODE_TDM_STZ 0x0020 -#define TSA_SIMODE_TDM_CE 0x0010 -#define TSA_SIMODE_TDM_FE 0x0008 -#define TSA_SIMODE_TDM_GM 0x0004 -#define TSA_SIMODE_TDM_TFSD(x) ((x) << 0) +#define TSA_SIMODE_SMC2 BIT(31) +#define TSA_SIMODE_SMC1 BIT(15) +#define TSA_SIMODE_TDMA_MASK GENMASK(11, 0) +#define TSA_SIMODE_TDMA(x) FIELD_PREP(TSA_SIMODE_TDMA_MASK, x) +#define TSA_SIMODE_TDMB_MASK GENMASK(27, 16) +#define TSA_SIMODE_TDMB(x) FIELD_PREP(TSA_SIMODE_TDMB_MASK, x) +#define TSA_SIMODE_TDM_MASK GENMASK(11, 0) +#define TSA_SIMODE_TDM_SDM_MASK GENMASK(11, 10) +#define TSA_SIMODE_TDM_SDM_NORM FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x0) +#define TSA_SIMODE_TDM_SDM_ECHO FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x1) +#define TSA_SIMODE_TDM_SDM_INTL_LOOP FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x2) +#define TSA_SIMODE_TDM_SDM_LOOP_CTRL FIELD_PREP_CONST(TSA_SIMODE_TDM_SDM_MASK, 0x3) +#define TSA_SIMODE_TDM_RFSD_MASK GENMASK(9, 8) +#define TSA_SIMODE_TDM_RFSD(x) FIELD_PREP(TSA_SIMODE_TDM_RFSD_MASK, x) +#define TSA_SIMODE_TDM_DSC BIT(7) +#define TSA_SIMODE_TDM_CRT BIT(6) +#define TSA_SIMODE_TDM_STZ BIT(5) +#define TSA_SIMODE_TDM_CE BIT(4) +#define TSA_SIMODE_TDM_FE BIT(3) +#define TSA_SIMODE_TDM_GM BIT(2) +#define TSA_SIMODE_TDM_TFSD_MASK GENMASK(1, 0) +#define TSA_SIMODE_TDM_TFSD(x) FIELD_PREP(TSA_SIMODE_TDM_TFSD_MASK, x) /* SI global mode register (8 bits) */ #define TSA_SIGMR 0x04 -#define TSA_SIGMR_ENB (1<<3) -#define TSA_SIGMR_ENA (1<<2) -#define TSA_SIGMR_RDM_MASK 0x03 -#define TSA_SIGMR_RDM_STATIC_TDMA 0x00 -#define TSA_SIGMR_RDM_DYN_TDMA 0x01 -#define TSA_SIGMR_RDM_STATIC_TDMAB 0x02 -#define TSA_SIGMR_RDM_DYN_TDMAB 0x03 +#define TSA_SIGMR_ENB BIT(3) +#define TSA_SIGMR_ENA BIT(2) +#define TSA_SIGMR_RDM_MASK GENMASK(1, 0) +#define TSA_SIGMR_RDM_STATIC_TDMA FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x0) +#define TSA_SIGMR_RDM_DYN_TDMA FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x1) +#define TSA_SIGMR_RDM_STATIC_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x2) +#define TSA_SIGMR_RDM_DYN_TDMAB FIELD_PREP_CONST(TSA_SIGMR_RDM_MASK, 0x3) /* SI status register (8 bits) */ #define TSA_SISTR 0x06 @@ -69,30 +75,33 @@ /* SI clock route register (32 bits) */ #define TSA_SICR 0x0C -#define TSA_SICR_SCC2(x) ((x) << 8) -#define TSA_SICR_SCC3(x) ((x) << 16) -#define TSA_SICR_SCC4(x) ((x) << 24) -#define TSA_SICR_SCC_MASK 0x0ff -#define TSA_SICR_SCC_GRX (1 << 7) -#define TSA_SICR_SCC_SCX_TSA (1 << 6) -#define TSA_SICR_SCC_RXCS_MASK (0x7 << 3) -#define TSA_SICR_SCC_RXCS_BRG1 (0x0 << 3) -#define TSA_SICR_SCC_RXCS_BRG2 (0x1 << 3) -#define TSA_SICR_SCC_RXCS_BRG3 (0x2 << 3) -#define TSA_SICR_SCC_RXCS_BRG4 (0x3 << 3) -#define TSA_SICR_SCC_RXCS_CLK15 (0x4 << 3) -#define TSA_SICR_SCC_RXCS_CLK26 (0x5 << 3) -#define TSA_SICR_SCC_RXCS_CLK37 (0x6 << 3) -#define TSA_SICR_SCC_RXCS_CLK48 (0x7 << 3) -#define TSA_SICR_SCC_TXCS_MASK (0x7 << 0) -#define TSA_SICR_SCC_TXCS_BRG1 (0x0 << 0) -#define TSA_SICR_SCC_TXCS_BRG2 (0x1 << 0) -#define TSA_SICR_SCC_TXCS_BRG3 (0x2 << 0) -#define TSA_SICR_SCC_TXCS_BRG4 (0x3 << 0) -#define TSA_SICR_SCC_TXCS_CLK15 (0x4 << 0) -#define TSA_SICR_SCC_TXCS_CLK26 (0x5 << 0) -#define TSA_SICR_SCC_TXCS_CLK37 (0x6 << 0) -#define TSA_SICR_SCC_TXCS_CLK48 (0x7 << 0) +#define TSA_SICR_SCC2_MASK GENMASK(15, 8) +#define TSA_SICR_SCC2(x) FIELD_PREP(TSA_SICR_SCC2_MASK, x) +#define TSA_SICR_SCC3_MASK GENMASK(23, 16) +#define TSA_SICR_SCC3(x) FIELD_PREP(TSA_SICR_SCC3_MASK, x) +#define TSA_SICR_SCC4_MASK GENMASK(31, 24) +#define TSA_SICR_SCC4(x) FIELD_PREP(TSA_SICR_SCC4_MASK, x) +#define TSA_SICR_SCC_MASK GENMASK(7, 0) +#define TSA_SICR_SCC_GRX BIT(7) +#define TSA_SICR_SCC_SCX_TSA BIT(6) +#define TSA_SICR_SCC_RXCS_MASK GENMASK(5, 3) +#define TSA_SICR_SCC_RXCS_BRG1 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x0) +#define TSA_SICR_SCC_RXCS_BRG2 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x1) +#define TSA_SICR_SCC_RXCS_BRG3 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x2) +#define TSA_SICR_SCC_RXCS_BRG4 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x3) +#define TSA_SICR_SCC_RXCS_CLK15 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x4) +#define TSA_SICR_SCC_RXCS_CLK26 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x5) +#define TSA_SICR_SCC_RXCS_CLK37 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x6) +#define TSA_SICR_SCC_RXCS_CLK48 FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x7) +#define TSA_SICR_SCC_TXCS_MASK GENMASK(2, 0) +#define TSA_SICR_SCC_TXCS_BRG1 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x0) +#define TSA_SICR_SCC_TXCS_BRG2 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x1) +#define TSA_SICR_SCC_TXCS_BRG3 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x2) +#define TSA_SICR_SCC_TXCS_BRG4 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x3) +#define TSA_SICR_SCC_TXCS_CLK15 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x4) +#define TSA_SICR_SCC_TXCS_CLK26 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x5) +#define TSA_SICR_SCC_TXCS_CLK37 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x6) +#define TSA_SICR_SCC_TXCS_CLK48 FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x7) /* Serial interface RAM pointer register (32 bits) */ #define TSA_SIRP 0x10