From patchwork Wed Aug 14 14:56:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mostafa Saleh X-Patchwork-Id: 13763600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B51F7C52D7D for ; Wed, 14 Aug 2024 14:58:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:Cc:To:From:Subject:Message-ID:Mime-Version:Date:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; 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d=google.com; s=20230601; t=1723647398; x=1724252198; darn=lists.infradead.org; h=content-transfer-encoding:cc:to:from:subject:message-id :mime-version:date:from:to:cc:subject:date:message-id:reply-to; bh=6QiimjaWFQigtWp7gc9RJ6NeS58KxDmWelajHEyqbgQ=; b=oBXNgeJkpSWX2d2hIPpILEArAzMVWFFaNlpxOKUC3ekqLAv1ZS/1c3g1I1YVBLJkdm CgKe3CWC7nD/7Xz0GDC678vgqkkHWKaFtPT58zVAWSTTagEwymdady6vAU13RmNKLbED sErxcsY13FgNfBYmKK4eo4EHa8pvwEDgGTEdLYXesui1TsOevKk+UfUwZdmMw511/XBO XlIBilC75Z2lvyDxUmqA0+0aOQq9rtzuAUsThs6kmzSlzuSoeYLLxftWsWcITPxjQteH uNnFRo/ih6sYiPgKP9FmeWdFgPBb3PF+gLxSHIdWRaUv00Mjtwo1hvlNmfaXj+yXkFO1 +4gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723647398; x=1724252198; h=content-transfer-encoding:cc:to:from:subject:message-id :mime-version:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=6QiimjaWFQigtWp7gc9RJ6NeS58KxDmWelajHEyqbgQ=; b=HfTplgNyPytvpj0EmzEkgApojUS8wNhJPyiBGJMXLHHOsJmHJlqIBoQQHbLWgJo6TM fTF6ZOuQPnoQdlCbdU9Emwijc5xs8b97SigZXykSF5Cl4qskCbOmNlvtXkGEWnoi1TJq J3lqGpDnOJ5SnLloLMOZ+7QiDdLEltaH5bEOUbR0Ny7kMGvbx+i2R1bvC5HPfQEzZ6Am eQLphFYceUAJusLIyGNCpBWDB1AeU1iR5Ef3u2sW1U0bWxKc4pC35pTbTnyFU5pJca33 BCIcP7jHUECpwaZ997uFWJWGWBBHJL/NJ/+HVwoBeC88j3UA47EOlVfq4ax71fru+fHL ztYA== X-Forwarded-Encrypted: i=1; AJvYcCWbX9upBVXzJXG4zDnMgz93eqbjRtQEOlH00VUNzHOanQc63dhnyRc9f7MxpLZSHQBhZDIZ7m93vf+SW/te2VjMwaKJs9tBiZIpg6JbNj7qVY5jf6I= X-Gm-Message-State: AOJu0Yyv/axouEXkVbBfuF97svKt63MXfeNjxrgd+4zSeQ8zfRmZ9MUY Z67GsKlmVbSfLpUOQ8FDq4lqNUxZ/TJ1uKQ33c2BYwhT07lf2TkwuT0u0uUTlG9mOVGBAFkfml8 ZNFsqfnWLew== X-Google-Smtp-Source: AGHT+IEwZKpbi2DVRDWHPR9t5KsZu510hTwOo8qGv7V3OsKoQsm3WmSQ4c6RbXYHvqRaHKRLcB9RJgCyn8fG3w== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a25:ed04:0:b0:e0b:bafe:a7f3 with SMTP id 3f1490d57ef6-e1155ba2f29mr125325276.11.1723647398061; Wed, 14 Aug 2024 07:56:38 -0700 (PDT) Date: Wed, 14 Aug 2024 14:56:33 +0000 Mime-Version: 1.0 X-Mailer: git-send-email 2.46.0.76.ge559c4bf1a-goog Message-ID: <20240814145633.2565126-1-smostafa@google.com> Subject: [PATCH v2] iommu/arm-smmu-v3: Match Stall behaviour for S2 From: Mostafa Saleh To: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: jean-philippe@linaro.org, jgg@ziepe.ca, nicolinc@nvidia.com, mshavit@google.com, Mostafa Saleh X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240814_075640_030889_38A6693D X-CRM114-Status: GOOD ( 18.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org According to the spec (ARM IHI 0070 F.b), in "5.5 Fault configuration (A, R, S bits)": A STE with stage 2 translation enabled and STE.S2S == 0 is considered ILLEGAL if SMMU_IDR0.STALL_MODEL == 0b10. Also described in the pseudocode “SteIllegal()” if eff_idr0_stall_model == '10' && STE.S2S == '0' then // stall_model forcing stall, but S2S == 0 return TRUE; Which means, S2S must be set when stall model is "ARM_SMMU_FEAT_STALL_FORCE", but at the moment the driver ignores that. Although, the driver can do the minimum and only set S2S for “ARM_SMMU_FEAT_STALL_FORCE”, it is more consistent to match S1 behaviour, which also sets it for “ARM_SMMU_FEAT_STALL” if the master has requested stalls. One caveat, is that S2S is not compatible with ATS, this mentioned in “5.2 Stream Table Entry”: In implementations of SMMUv3.1 and later, this configuration is ILLEGAL if EATS is not IGNORED and Config[1] == 1 and S2S == 1. In SMMUv3.0 implementations, this configuration is ILLEGAL if EATS is not IGNORED and S2S == 1 This is also described in the pseudocode “SteIllegal()” Also, since S2 stalls are enabled now, report them to the IOMMU layer and for VFIO devices it will fail anyway as VFIO doesn’t register an iopf handler. Signed-off-by: Mostafa Saleh --- v2: - Fix index of the STE - Fix conflict with ATS - Squash the 2 patches and drop enable_nesting --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 ++++++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a31460f9f3d4..3b70816a2b81 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1601,6 +1601,14 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, target->data[2] = cpu_to_le64(FIELD_PREP(STRTAB_STE_2_S2VMID, 0)); } + + /* + * S2S is ignored if stage-2 exists but not enabled. + * S2S is not compatible with ATS. + */ + if (master->stall_enabled && !ats_enabled && + smmu->features & ARM_SMMU_FEAT_TRANS_S2) + target->data[2] |= STRTAB_STE_2_S2S; } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); @@ -1739,10 +1747,6 @@ static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt) return -EOPNOTSUPP; } - /* Stage-2 is always pinned at the moment */ - if (evt[1] & EVTQ_1_S2) - return -EFAULT; - if (!(evt[1] & EVTQ_1_STALL)) return -EOPNOTSUPP; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 14bca41a981b..0dc7ad43c64c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -267,6 +267,7 @@ struct arm_smmu_ste { #define STRTAB_STE_2_S2AA64 (1UL << 51) #define STRTAB_STE_2_S2ENDI (1UL << 52) #define STRTAB_STE_2_S2PTW (1UL << 54) +#define STRTAB_STE_2_S2S (1UL << 57) #define STRTAB_STE_2_S2R (1UL << 58) #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)