@@ -54,6 +54,14 @@ gic_its: msi-controller@1820000 {
};
};
+ main_esm: esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x700000 0x00 0x1000>;
+ /* Interrupt sources: rti0, rti1, rti2, rti3 */
+ ti,esm-pins = <224>, <225>, <226>, <227>;
+ bootph-pre-ram;
+ };
+
serdes0: serdes@900000 {
compatible = "ti,phy-am654-serdes";
reg = <0x0 0x900000 0x0 0x2000>;
@@ -440,6 +440,14 @@ mcu_r5fss0_core1: r5f@41400000 {
};
};
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ /* Interrupt sources: mrti0, mrti1 */
+ ti,esm-pins = <104>, <105>;
+ bootph-pre-ram;
+ };
+
mcu_rti1: watchdog@40610000 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x40610000 0x0 0x100>;
Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt Sources. There are no ESM0_ESM_INT* events routed to MCU ESM, so it is not possible to reset the CPU using watchdog and ESM0 configuration. However add ESM instances for device completion. Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf Signed-off-by: Judith Mendez <jm@ti.com> --- Changes since v2: - Fix commit message for patch 6/6 --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+)