diff mbox series

[v2,09/14] arm64: dts: freescale: imx93-tqma9352-mba93xxca: add RTC / temp sensor IRQ

Message ID 20240819120328.229622-10-alexander.stein@ew.tq-group.com (mailing list archive)
State New, archived
Headers show
Series TQMa93xx improvements | expand

Commit Message

Alexander Stein Aug. 19, 2024, 12:03 p.m. UTC 
From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

The IRQ lines from devices on SoM are connected to CPU GPIO on
this mainboard.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxca.dts    | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 9673b93ba4702..74e1347e25ea8 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -495,6 +495,22 @@  &lpuart8 {
 	status = "okay";
 };
 
+&pcf85063 {
+	/* RTC_EVENT# from SoM is connected on mainboard */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcf85063>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&se97_som {
+	/* TEMP_EVENT# from SoM is connected on mainboard */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_temp_sensor_som>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+};
+
 &tpm5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_tpm5>;
@@ -653,6 +669,12 @@  MX93_PAD_GPIO_IO03__LPSPI6_SCK		0x3fe
 		>;
 	};
 
+	pinctrl_pcf85063: pcf85063grp {
+		fsl,pins = <
+			MX93_PAD_SAI1_RXD0__GPIO1_IO14			0x1000
+		>;
+	};
+
 	pinctrl_pexp_irq: pexpirqgrp {
 		fsl,pins = <
 			MX93_PAD_SAI1_TXC__GPIO1_IO12		0x1306
@@ -665,6 +687,13 @@  MX93_PAD_GPIO_IO09__GPIO2_IO09		0x1306
 		>;
 	};
 
+	pinctrl_temp_sensor_som: tempsensorsomgrp {
+		fsl,pins = <
+			/* HYS | FSEL_0 | no DSE */
+			MX93_PAD_SAI1_TXFS__GPIO1_IO11			0x1000
+		>;
+	};
+
 	pinctrl_tpm5: tpm5grp {
 		fsl,pins = <
 			MX93_PAD_GPIO_IO06__TPM5_CH0		0x57e