diff mbox series

[v2,14/14] arm64: dts: freescale: imx93-tqma9352: set SION for cmd and data pad of USDHC

Message ID 20240819120328.229622-15-alexander.stein@ew.tq-group.com (mailing list archive)
State New, archived
Headers show
Series TQMa93xx improvements | expand

Commit Message

Alexander Stein Aug. 19, 2024, 12:03 p.m. UTC 
From: Markus Niebel <Markus.Niebel@ew.tq-group.com>

imx93 pad integrate has one issue, refer to ERR052021:

ERR052021 uSDHC: Sometimes uSDHC does not work under VDD_SOC low
		 drive mode and nominal mode
Description:
uSDHC PADs have one integration issue.
When CMD/DATA lines direction change from output to input, uSDHC
controller begin sampling, the integration issue will make input
enable signal from uSDHC propagated to the PAD with a long delay,
thus the new input value on the pad comes to uSDHC lately. The
uSDHC sampled the old input value and the sampling result is wrong.

Workaround:
Set uSDHC CMD/DATA PADs iomux register SION bit to 1, then PADs will
propagate input to uSDHC with no delay, so correct value is sampled.

This issue will wrongly trigger the start bit when sample the USDHC
command response, cause the USDHC trigger command CRC/index/endbit
error, which will finally impact the tuning pass window, espically
will impact the standard tuning logic, and can't find a correct delay
cell to get the best timing.

This follows changes made for i.MX93 EVK with commit bb89601282fc ("arm64:
dts: imx93-11x11-evk: set SION for cmd and data pad of USDHC")

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 .../freescale/imx93-tqma9352-mba93xxca.dts    | 22 ++++++++++---------
 .../freescale/imx93-tqma9352-mba93xxla.dts    | 22 ++++++++++---------
 .../boot/dts/freescale/imx93-tqma9352.dtsi    | 19 ++++++++--------
 3 files changed, 34 insertions(+), 29 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
index 79b9f13de4af5..599df32976e24 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
@@ -870,32 +870,34 @@  MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_hs: usdhc2hsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X5 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
 			/* HYS | PU | FSEL_3 | DSE X3 */
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X6 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
index 3f8726180bba2..0b4b3bb866d06 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
@@ -832,32 +832,34 @@  MX93_PAD_SD2_CD_B__GPIO3_IO00			0x1000
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_hs: usdhc2hsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X5 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05be
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
 			/* HYS | PU | FSEL_3 | DSE X3 */
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000138e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000138e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000138e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000138e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc2_uhs: usdhc2uhsgrp {
 		fsl,pins = <
 			/* PD | FSEL_3 | DSE X6 */
 			MX93_PAD_SD2_CLK__USDHC2_CLK			0x05fe
 			/* HYS | PU | FSEL_3 | DSE X4 */
-			MX93_PAD_SD2_CMD__USDHC2_CMD			0x139e
-			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x139e
-			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x139e
-			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x139e
-			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x139e
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x4000139e
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x4000139e
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1		0x4000139e
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2		0x4000139e
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3		0x4000139e
 			/* FSEL_2 | DSE X3 */
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x010e
 		>;
diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
index 48ba60832eb3e..2cabdae242273 100644
--- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
@@ -270,6 +270,7 @@  MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x106
 		>;
 	};
 
+	/* enable SION for data and cmd pad due to ERR052021 */
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			/* PD | FSEL 3 | DSE X5 */
@@ -277,16 +278,16 @@  MX93_PAD_SD1_CLK__USDHC1_CLK		0x5be
 			/* HYS | FSEL 0 | no drive */
 			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1000
 			/* HYS | FSEL 3 | X5 */
-			MX93_PAD_SD1_CMD__USDHC1_CMD		0x11be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400011be
 			/* HYS | FSEL 3 | X4 */
-			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x119e
-			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x119e
-			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x119e
-			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x119e
-			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x119e
-			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x119e
-			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x119e
-			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x119e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000119e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000119e
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000119e
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000119e
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000119e
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000119e
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000119e
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000119e
 		>;
 	};