| Message ID | 20240820-qcom_ipq_cmnpll-v2-3-b000dd335280@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add CMN PLL clock controller driver for IPQ9574 | expand |
On Tue, Aug 20, 2024 at 10:02:44PM +0800, Luo Jie wrote: > The CMN PLL hardware block is available in the Qualcomm IPQ SoC such > as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet > related hardware blocks such as external Ethernet PHY or switch. This > driver is initially being enabled for IPQ9574. All boards based on > IPQ9574 SoC will require to include this driver in the build. > > This CMN PLL hardware block does not provide any other specific function > on the IPQ SoC other than enabling output clocks to Ethernet related > devices. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 01dd286ba7ef..1bc7bd86e589 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y
The CMN PLL hardware block is available in the Qualcomm IPQ SoC such as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. This CMN PLL hardware block does not provide any other specific function on the IPQ SoC other than enabling output clocks to Ethernet related devices. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)