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Wed, 21 Aug 2024 01:29:33 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 21 Aug 2024 16:28:55 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 21 Aug 2024 16:28:54 +0800 From: friday.yang To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: Yong Wu , Philipp Zabel , Friday Yang , , , , , Subject: [PATCH 1/4] dt-bindings: memory: mediatek: Add mt8188 SMI reset control binding Date: Wed, 21 Aug 2024 16:26:49 +0800 Message-ID: <20240821082845.11792-2-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240821082845.11792-1-friday.yang@mediatek.com> References: <20240821082845.11792-1-friday.yang@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.829500-8.000000 X-TMASE-MatchedRID: R3B6Edw+gpAxFdXyW/P+XcnUT+eskUQPLEOkDuO6MI8km/L/MIL+8pM5 rPAxB6p1lTJXKqh1ne1M8qdoCvOVvms/tFw6ZTQWuIwLnB3Aqp2WHGENdT+VP5uc2X2zst+xDrG 3Q1PIT6iJh4lfRksIUHAdyhB0oDzs9mia1kFQhdCQ+GmkZu94cv+UEb65dgmQ+5+93dPb6/eAzY IjHF+VJeLzNWBegCW2U9w4XVXDWCYLbigRnpKlKTpcQTtiHDgWQxitkXat1SEypeIkTB5qDJNG+ ExD2vU/Pay9KaxQKp7x9BkkBFqz7g== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.829500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: BBD090C5ECD942BC4A586DC9F9181C138D2C8BE75586C512F0FFFF14353E0B132000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_012938_931109_30F12C55 X-CRM114-Status: GOOD ( 15.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support SMI clamp and reset operation in genpd callback, add SMI LARB reset register offset and mask related information in the bindings. Add index in mt8188-resets.h to query the register offset and mask in the SMI reset control driver. Signed-off-by: friday.yang --- .../bindings/reset/mediatek,smi-reset.yaml | 46 +++++++++++++++++++ include/dt-bindings/reset/mt8188-resets.h | 11 +++++ 2 files changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml new file mode 100644 index 000000000000..66ac121d2396 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek,smi-reset.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2024 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek,smi-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SMI Reset Controller + +maintainers: + - Friday Yang + +description: | + This reset controller node is used to perform reset management + of SMI larbs on MediaTek platform. It is used to implement various + reset functions required when SMI larbs apply clamp operation. + + For list of all valid reset indices see + for MT8188. + +properties: + compatible: + enum: + - mediatek,smi-reset-mt8188 + + "#reset-cells": + const: 1 + + mediatek,larb-rst-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of the SMI larb's reset controller syscon. + +required: + - compatible + - "#reset-cells" + - mediatek,larb-rst-syscon + +additionalProperties: false + +examples: + - | + imgsys1_dip_top_rst: reset-controller { + compatible = "mediatek,smi-reset-mt8188"; + #reset-cells = <1>; + mediatek,larb-rst-syscon = <&imgsys1_dip_top>; + }; diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 5a58c54e7d20..387a4beac688 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -113,4 +113,15 @@ #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 +#define MT8188_SMI_RST_LARB10 0 +#define MT8188_SMI_RST_LARB11A 1 +#define MT8188_SMI_RST_LARB11C 2 +#define MT8188_SMI_RST_LARB12 3 +#define MT8188_SMI_RST_LARB11B 4 +#define MT8188_SMI_RST_LARB15 5 +#define MT8188_SMI_RST_LARB16B 6 +#define MT8188_SMI_RST_LARB17B 7 +#define MT8188_SMI_RST_LARB16A 8 +#define MT8188_SMI_RST_LARB17A 9 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */