diff mbox series

[BOOT-WRAPPER,v3,04/10] aarch32: Refactor inital entry

Message ID 20240822101441.251184-5-mark.rutland@arm.com (mailing list archive)
State New, archived
Headers show
Series Cleanup initialization | expand

Commit Message

Mark Rutland Aug. 22, 2024, 10:14 a.m. UTC 
For historical reasons the early AArch32 code is structured differently
from the early AArch64 code, with some common code (including stack
setup) performed before we identify the mode we were entered in.

Align the structure of the early AArch32 code with that of the early
AArch64 code. This will make subsequent refactoring easier.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Akos Denke <akos.denke@arm.com>
Cc: Luca Fancellu <luca.fancellu@arm.com>
---
 arch/aarch32/boot.S | 55 ++++++++++++++++++++++++++++-----------------
 1 file changed, 34 insertions(+), 21 deletions(-)
diff mbox series

Patch

diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S
index 4d16c9c..cf83e55 100644
--- a/arch/aarch32/boot.S
+++ b/arch/aarch32/boot.S
@@ -31,7 +31,28 @@ 
 	 *   PSCI is not supported when entered in this mode.
 	 */
 ASM_FUNC(_start)
-	/* Stack initialisation */
+	mrs	r0, cpsr
+	and	r0, #PSR_MODE_MASK
+	cmp	r0, #PSR_SVC
+	beq	reset_at_svc
+	cmp	r0, #PSR_HYP
+	beq	reset_at_hyp
+
+	/* Booting at other modes is not supported */
+	b	.
+
+reset_at_svc:
+	/*
+	 * When entered in Secure SVC mode we must switch to monitor mode to
+	 * configure SCR.NS. Switch to monitor mode ASAP to simplify later
+	 * code.
+	 */
+	adr	lr, reset_at_mon
+	ldr	r0, =(PSR_A | PSR_I | PSR_F | PSR_MON)
+	msr	spsr, r0
+	movs	pc, lr
+
+reset_at_mon:
 	cpuid	r0, r1
 	bl	find_logical_id
 	cmp	r0, #MPIDR_INVALID
@@ -39,36 +60,28 @@  ASM_FUNC(_start)
 
 	bl	setup_stack
 
-	mrs	r0, cpsr
-	and	r0, #PSR_MODE_MASK
-
-	cmp	r0, #PSR_HYP
-	bne	_switch_monitor
+	bl	cpu_init_bootwrapper
 
-	mov	r0, #1
-	ldr	r1, =flag_no_el3
-	str	r0, [r1]
+	bl	cpu_init_secure_pl1
 
-	bl	cpu_init_bootwrapper
+	bl	gic_secure_init
 
 	b	start_bootmethod
 
-_switch_monitor:
-	adr	lr, _monitor
-	ldr	r0, =(PSR_A | PSR_I | PSR_F | PSR_MON)
-	msr	spsr, r0
-	movs	pc, lr
+reset_at_hyp:
+	cpuid	r0, r1
+	bl	find_logical_id
+	cmp	r0, #MPIDR_INVALID
+	beq	err_invalid_id
 
-_monitor:
-	/* Move the stack to Monitor mode*/
-	mrs	sp, sp_svc
+	bl	setup_stack
 
-	bl	cpu_init_secure_pl1
+	mov	r0, #1
+	ldr	r1, =flag_no_el3
+	str	r0, [r1]
 
 	bl	cpu_init_bootwrapper
 
-	bl	gic_secure_init
-
 	b	start_bootmethod
 
 err_invalid_id: