| Message ID | 20240822151113.1479789-5-joey.gouly@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Permission Overlay Extension | expand |
On Thu, Aug 22, 2024 at 04:10:47PM +0100, Joey Gouly wrote: > Allow EL0 or EL1 to access POR_EL0 without being trapped to EL2. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/el2_setup.h | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git arch/arm64/include/asm/el2_setup.h arch/arm64/include/asm/el2_setup.h > index fd87c4b8f984..212191ecad40 100644 > --- arch/arm64/include/asm/el2_setup.h > +++ arch/arm64/include/asm/el2_setup.h > @@ -185,12 +185,20 @@ > .Lset_pie_fgt_\@: > mrs_s x1, SYS_ID_AA64MMFR3_EL1 > ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 > - cbz x1, .Lset_fgt_\@ > + cbz x1, .Lset_poe_fgt_\@ > > /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ > orr x0, x0, #HFGxTR_EL2_nPIR_EL1 > orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 > > +.Lset_poe_fgt_\@: > + mrs_s x1, SYS_ID_AA64MMFR3_EL1 > + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 > + cbz x1, .Lset_fgt_\@ > + > + /* Disable trapping of POR_EL0 */ > + orr x0, x0, #HFGxTR_EL2_nPOR_EL0 Dave's reworking the labels here on for-next/misc: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/commit/?h=for-next/misc&id=5b39db6037e7cba1659f2149aef76934370aa6d5 Please can you follow that new style for the new label so that we don't end up with an immediate inconsistency? Leave the '.Lset_fgt' label as-is and I'll fix it when we merge the branches. Cheers, Will
diff --git arch/arm64/include/asm/el2_setup.h arch/arm64/include/asm/el2_setup.h index fd87c4b8f984..212191ecad40 100644 --- arch/arm64/include/asm/el2_setup.h +++ arch/arm64/include/asm/el2_setup.h @@ -185,12 +185,20 @@ .Lset_pie_fgt_\@: mrs_s x1, SYS_ID_AA64MMFR3_EL1 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 - cbz x1, .Lset_fgt_\@ + cbz x1, .Lset_poe_fgt_\@ /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ orr x0, x0, #HFGxTR_EL2_nPIR_EL1 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 +.Lset_poe_fgt_\@: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1POE_SHIFT, #4 + cbz x1, .Lset_fgt_\@ + + /* Disable trapping of POR_EL0 */ + orr x0, x0, #HFGxTR_EL2_nPOR_EL0 + .Lset_fgt_\@: msr_s SYS_HFGRTR_EL2, x0 msr_s SYS_HFGWTR_EL2, x0