From patchwork Tue Aug 27 16:44:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 13779815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30B72C54731 for ; Tue, 27 Aug 2024 16:49:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/s/MkzV79yX08qnUXJHy4ScLNLNGb2tsS4HwoA6pEQw=; b=uwBrwH4FUlPzQ4VTdmnYJJJyEO p+sKgYxrHT69KZ5HcXlgd0aXF/KN6wkNlRGRZ1uBzoakDRQItJ7oaxEUYLNy0e132JWa7BdJtDTko kv5C7WPEJpKKe9feex3zZ6JBr0e5EyDXPLeNhUOXK3ed9N4i1APUWHuIb/oQ+oGmPkuIyytjQjPH0 wHHs3ZpQ22zaaEUpJ/OWHtCSbUKtcjnJTdyZdsP2OOK12SPW3PTbhadEyQIJkybpBJUb08YGfesib uAxSHx4ZgUv5IbWtzVyfYhafXSkpnxPudq8VRsMT6Iq2d4JgSQqPnMCNrj5aW6spuX9W3oXjTv2Ix /ooizguw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sizNv-0000000C8lm-2niH; Tue, 27 Aug 2024 16:49:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sizJF-0000000C7YH-24TT for linux-arm-kernel@lists.infradead.org; Tue, 27 Aug 2024 16:44:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4673FDA7; Tue, 27 Aug 2024 09:45:11 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ED06A3F762; Tue, 27 Aug 2024 09:44:42 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Will Deacon , Mark Rutland , Suzuki K Poulose , Mike Leach , James Clark , John Garry , Namhyung Kim , Ian Rogers , Adrian Hunter , "Liang, Kan" , Jonathan Cameron , Yicong Yang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-perf-users@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 5/9] perf arm-spe: Extend meta data header for version 2 Date: Tue, 27 Aug 2024 17:44:13 +0100 Message-Id: <20240827164417.3309560-6-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240827164417.3309560-1-leo.yan@arm.com> References: <20240827164417.3309560-1-leo.yan@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240827_094445_658624_D8247426 X-CRM114-Status: GOOD ( 16.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This commit extends the meta data header structure for version 2. The first version's header structure doesn't include a field to indicate the header's version, adds a new field for it. And extends to support per CPU's meta data. Add macros for metadata header size and per CPU data size, and update the code with these macros. No functional change. Signed-off-by: Leo Yan --- tools/perf/arch/arm64/util/arm-spe.c | 4 ++-- tools/perf/util/arm-spe.c | 2 +- tools/perf/util/arm-spe.h | 34 +++++++++++++++++++++++++++- 3 files changed, 36 insertions(+), 4 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index 7880190c3dd6..3e7f62bac2e0 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -42,7 +42,7 @@ static size_t arm_spe_info_priv_size(struct auxtrace_record *itr __maybe_unused, struct evlist *evlist __maybe_unused) { - return ARM_SPE_AUXTRACE_PRIV_SIZE; + return ARM_SPE_AUXTRACE_V1_PRIV_SIZE; } static int arm_spe_info_fill(struct auxtrace_record *itr, @@ -54,7 +54,7 @@ static int arm_spe_info_fill(struct auxtrace_record *itr, container_of(itr, struct arm_spe_recording, itr); struct perf_pmu *arm_spe_pmu = sper->pmu[0]; - if (priv_size != ARM_SPE_AUXTRACE_PRIV_SIZE) + if (priv_size != ARM_SPE_AUXTRACE_V1_PRIV_SIZE) return -EINVAL; if (!session->evlist->core.nr_mmaps) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 3f8695fe6a20..1e87342f4bd8 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -1260,7 +1260,7 @@ int arm_spe_process_auxtrace_info(union perf_event *event, struct perf_session *session) { struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; - size_t min_sz = sizeof(u64) * ARM_SPE_AUXTRACE_PRIV_MAX; + size_t min_sz = ARM_SPE_AUXTRACE_V1_PRIV_SIZE; struct perf_record_time_conv *tc = &session->time_conv; const char *cpuid = perf_env__cpuid(session->evlist->env); u64 midr = strtol(cpuid, NULL, 16); diff --git a/tools/perf/util/arm-spe.h b/tools/perf/util/arm-spe.h index e1327e1b3fec..5d587a8e3cf8 100644 --- a/tools/perf/util/arm-spe.h +++ b/tools/perf/util/arm-spe.h @@ -12,10 +12,42 @@ enum { ARM_SPE_PMU_TYPE, ARM_SPE_PER_CPU_MMAPS, + /* + * The initial version doesn't have version number, so version 1 is + * reserved and the header version starts from 2. + */ + ARM_SPE_HEADER_VERSION, + ARM_SPE_CPU_NUM, ARM_SPE_AUXTRACE_PRIV_MAX, }; -#define ARM_SPE_AUXTRACE_PRIV_SIZE (ARM_SPE_AUXTRACE_PRIV_MAX * sizeof(u64)) +enum { + ARM_SPE_CPU, + ARM_SPE_CPU_MIDR, + ARM_SPE_CPU_PMU_TYPE, + ARM_SPE_CAP_MIN_IVAL, + ARM_SPE_CAP_LDS, + ARM_SPE_PER_CPU_PRIV_MAX, +}; + +#define ARM_SPE_HEADER_CURRENT_VERSION 2 + +#define ARM_SPE_METADATA_SIZE(cnt) ((cnt) * sizeof(u64)) + +#define ARM_SPE_AUXTRACE_V1_PRIV_MAX \ + (ARM_SPE_PER_CPU_MMAPS + 1) +#define ARM_SPE_AUXTRACE_V1_PRIV_SIZE \ + ARM_SPE_METADATA_SIZE(ARM_SPE_AUXTRACE_V1_PRIV_MAX) + +#define ARM_SPE_AUXTRACE_V2_PRIV_MAX \ + (ARM_SPE_CPU_NUM + 1) +#define ARM_SPE_AUXTRACE_V2_PRIV_SIZE \ + ARM_SPE_METADATA_SIZE(ARM_SPE_AUXTRACE_V2_PRIV_MAX) + +#define ARM_SPE_AUXTRACE_V2_PRIV_PER_CPU_MAX \ + (ARM_SPE_CAP_LDS + 1) +#define ARM_SPE_AUXTRACE_V2_PER_CPU_SIZE \ + ARM_SPE_METADATA_SIZE(ARM_SPE_AUXTRACE_V2_PRIV_PER_CPU_MAX) union perf_event; struct perf_session;