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[v5,1/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock

Message ID 20240829082830.56959-2-quic_varada@quicinc.com (mailing list archive)
State New, archived
Headers show
Series Add NSS clock controller support for Qualcomm IPQ5332 | expand

Commit Message

Varadarajan Narayanan Aug. 29, 2024, 8:28 a.m. UTC 
From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>

Add the definition for GPLL0_OUT_AUX clock. This acts as the parent
for the certain networking subsystem (NSS) clocks.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v5: Update commit message to include why this clock is needed
---
 include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0a96d0..24486eb47ed8 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -179,6 +179,7 @@ 
 #define GCC_PCIE3X1_0_PIPE_CLK_SRC			170
 #define GCC_PCIE3X1_1_PIPE_CLK_SRC			171
 #define GCC_USB0_PIPE_CLK_SRC				172
+#define GPLL0_OUT_AUX					173
 
 #define GCC_ADSS_BCR					0
 #define GCC_ADSS_PWM_CLK_ARES				1